Philips Semiconductors
Remote 8-bit I/O expander for I2C-bus
5 PINNING
5.1 DIP16 and SO16 packages
SYMBOL
A0
A1
A2
P0
P1
P2
P3
VSS
P4
P5
P6
P7
INT
SCL
SDA
VDD
PIN
1 address input 0
2 address input 1
3 address input 2
4 quasi-bidirectional I/O 0
5 quasi-bidirectional I/O 1
6 quasi-bidirectional I/O 2
7 quasi-bidirectional I/O 3
8 supply ground
9 quasi-bidirectional I/O 4
10 quasi-bidirectional I/O 5
11 quasi-bidirectional I/O 6
12 quasi-bidirectional I/O 7
13 interrupt output (active LOW)
14 serial clock line
15 serial data line
16 supply voltage
DESCRIPTION
Product specification
PCF8574
handbook, halfpage
A0 1
16 VDD
A1 2
15 SDA
A2 3
14 SCL
P0 4 PCF8574P 13 INT
P1 5 PCF8574AP 12 P7
P2 6
11 P6
P3 7
VSS 8
10 P5
9 P4
MBD979
Fig.2 Pin configuration (DIP16).
handbook, halfpage
A0 1
A1 2
A2 3
P0 4
P1 5
P2 6
P3 7
VSS 8
16 VDD
15 SDA
14 SCL
PCF8574T 13 INT
PCF8574AT 12 P7
11 P6
10 P5
9 P4
MCE001
Fig.3 Pin configuration (SO16).
2002 Nov 22
5
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slave address (PCF8574)
data from port
SDA
S 0 1 0 0 A2 A1 A0 1 A
DATA 1
READ FROM
PORT
start condition
R/W acknowledge
from slave
DATA INTO
PORT
INT
t iv
DATA 2
t ph
t ir
DATA 3
data from port
A
acknowledge
from slave
DATA 4
t ps
t ir
DATA 4
1P
stop
condition
MBD975
A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the stop condition (P). Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present
at the last acknowledge phase is valid (output mode). Input data is lost.
Fig.12 READ mode (input).