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PDF Pm25LD512 Data sheet ( Hoja de datos )
| Número de pieza | Pm25LD512 | |
| Descripción | 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory | |
| Fabricantes | Chingis Technology | |
| Logotipo |  |
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512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial
Flash Memory With 100 MHz Dual-Output SPI Bus
Interface
Pm25LD512/010/ 020
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.3 V – 3.6 V
• Memory Organization
- Pm25LD512: 64K x 8 (512 Kbit)
- Pm25LD010: 128K x 8 (1 Mbit)
- Pm25LD020: 256K x 8 (2 Mbit)
• Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4KByte sectors / Two uniform
32KByte blocks
- 1Mb : Uniform 4KByte sectors / Four uniform
32KByte blocks
- 2Mb : Uniform 4KByte sectors / Four uniform
64KByte blocks
• Low standby current 1uA (Typ)
• Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
• Sector, Block or Chip Erase Operation
- Maximum 10 ms sector, block or chip erase
• Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
• Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow
partial or entire memory to be configured as read-
only
• High Product Endurance
- Guaranteed 200,000 program/erase cycles per
single sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LD040
- 8-pin 300mil PDIP for Pm25LD040
- 8-contact WSON
- 8-pin TSSOP
- Lead-free (Pb-free), halogen-free package
GENERAL DESCRIPTION
The Pm25LD512/010/020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing
single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100
MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating
voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The Pm25LD512/010/020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output
(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all
recognized command codes and operations. The dual-output fast read operation provides and effective serial
data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in
one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte
blocks.(Pm25LD020 is uniform 4 KByte sectors or uniform 64 KByte).
The Pm25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures
between -40°C to +105°C.
Confidential information
Chingis Technology Corp.
1 DRAFT Date: August, 2010, Rev:0.4
1 page  
Pm25LD512/010/ 020
SPI MODES DESCRIPTION
Multiple Pm25LD512/010/020 devices can be
connected on the SPI serial bus and controlled by a
SPI Master, i.e. microcontroller, as shown in Figure 1.
The devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SPI Interface with
(0,0) or (1,1)
SDIO
SDI
SCK
SPI Master
(i.e. Microcontroller)
CS3 CS2 CS1
SCK SO SIO
SCK SO SIO
SCK SO SIO
SPI Memory
Device
CE# WP#
HOLD#
SPI Memory
Device
CE# WP#
HOLD#
SPI Memory
Device
CE# WP#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
Figure 2. SPI Modes Supported
SCK
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SIO
Input mode
SO
MSb
Confidential information
Chingis Technology Corp.
MSb
5 DRAFT Date: August, 2010, Rev:0.4
5 Page 
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT
IDENTIFICATION) OPERATION
The Read Product Identification (RDID) instruction is
for reading out the old style of 8-bit Electronic
Table 11. Product Identification
Signature, whose values are shown as table of ID
Definitions. This is not same as RDID or JEDEC ID
Product Identification
instruction. It’s not recommended to use for new
design. For new design, please use RDID or JEDEC ID
instruction.
First Byte
Manufacturer ID
Second Byte
The RDES instruction code is followed by three dummy Device ID:
Device ID 1
bytes, each bit being latched-in on SI during the rising
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
Pm25LD512
Pm25LD010
05h
10h
falling edge of SCK. The RDES instruction is ended by
Pm25LD020
11h
CE# goes high. The Device ID outputs repeatedly if
continuously send the additional clock cycles on SCK
while CE# is at low.
Data
9Dh
7Fh
Device ID 2
20h
21h
22h
Figure 3. Read Product Identification Sequence
CE#
SCK
SI
01
78 9
31
INSTRUCTION
1010 1011b
3 Dummy Bytes
38 39
46 47
54
HIGH IMPEDANCE
SO
Device ID1
Device ID1
Device ID1
Confidential information
Chingis Technology Corp.
11 DRAFT Date: August, 2010, Rev:0.4
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet Pm25LD512.PDF ] | |
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