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PDF MT9J003 Data sheet ( Hoja de datos )
| Número de pieza | MT9J003 | |
| Descripción | 1/2.3-Inch 10Mp CMOS Digital Image Sensor | |
| Fabricantes | Aptina Imaging Corporation | |
| Logotipo |  |
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Aptina Confidential and Proprietary
MT9J003: 1/2.3-Inch 10Mp CMOS Digital Image Sensor
Features
1/2.3-Inch 10Mp CMOS Digital Image Sensor
MT9J003 Data Sheet
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
Features
• 1080p digital video mode
• Simple two-wire serial interface
• Auto black level calibration
• Support for external mechanical shutter
• Support for external LED or xenon flash
• High frame rate preview mode with arbitrary down-
size scaling from maximum resolution
• Programmable controls: gain, horizontal and vertical
blanking, auto black level offset correction, frame
size/rate, exposure, left–right and top–bottom image
reversal, window size, and panning
• Data interfaces: parallel or four-lane serial high-speed
pixel interface (HiSPi™) differential signaling (sub-
LVDS)
• On-die phase-locked loop (PLL) oscillator
• Bayer pattern downsize scaler
• Integrated position-based color and lens shading
correction
• One-time programmable memory (OTPM) for storing
module information
Applications
• Digital video cameras
• Digital still cameras
General Description
The Aptina MT9J003 is a 1/2.3-inch CMOS active-pixel
digital imaging sensor with an active pixel array of
3856H x 2764V including border pixels. It can support 10
megapixel (3664H x 2748V) digital still images and a
1080p (3840H x 2160V) digital video mode. It incorpo-
rates sophisticated on-chip camera functions such as
windowing, mirroring, column and row skip modes, and
snapshot mode. It is programmable through a simple
two-wire serial interface and has very low power con-
sumption.
Ordering Information
Table 1:
Available Part Numbers
Part Number
Description
MT9J003I12STCV2
MT9J003T12STCV
MT9J003D00STCV C2CBC1
MT9J003I12STCU
MT9J003D00STCU C2CBC1
HiSPi 48-pin iLCC, 0° CRA
HiSPi 48-pin tPLCC, 13.4° CRA
HiSPi Bare Die, 0° CRA
Parallel 48-pin iLCC, 0° CRA
Parallel Bare die, 0° CRA
Table 2:
Key Performance Parameters
Parameter
Optical format
Active imager size
Active pixels
Pixel size
Chief ray angle
Color filter array
Shutter type
Input clock frequency
Maxi- Parallel
mum HiSPi (4-lane)
data
rate
Still mode, 4:3
(3664H x 2748V)
Frame Preview mode
rate VGA
1080p mode
(1920H x 1080V)
ADC resolution
Responsivity
Dynamic range
SNRMAX
I/O Digital
Supply
voltage Digital
Analog
SLVS I/O
Power Still mode at 15fps
Con- w/ serial I/F
sump- Still mode at 7.5fps
tion w/ parallel I/F
Preview
Standby
Package
Operating temperature
Value
1/2.3-inch (4:3)
6.440mm(H) x 4.616mm (V),
7.923mm diagonal (Entire sensor)
6.119mm(H) x 4.589mm (V),
7.649mm diagonal (Still mode)
6.413mm(H) x 3.607mm (V),
7.358mm diagonal (Video mode)
3856H x 2764V (Entire sensor)
3664H x 2748V (4:3, Still mode)
3840H x 2160V (16:9, Video mode)
1.67 x 1.67μm
0°, 13.4°
RGB Bayer pattern
Electronic rolling shutter (ERS)
with global reset release (GRR)
6–48 MHz
80 Mp/s at 80 MHz PIXCLK
2.8Gbps
Programmable up to 15 fps serial
I/F, 7.5 fps parallel I/F
30 fps with binning
60 fps with skip2bin2
60 fps using HiSPi I/F
30 fps using parallel I/F
12-bit, on-die
0.31 V/lux-sec (550nm)
65.2dB
34dB
1.7–1.9V (1.8V nominal)
or 2.4–3.1V (2.8V nominal)
1.7–1.9V (1.8V nominal)
2.4–3.1V (2.8V nominal)
0.4 - 0.8V (0.4 or 0.8V nominal)
638mW
388mW
250mW low power VGA
500μW (typical, EXTCLK disabled)
48-pin iLCC (10mm x 10mm)
Bare die,
48pin Tiny PLCC (12mm x 12mm)
–30°C to +70°C (at junction)
PDF: 4791388811 Source: 9166348326
MT9J003-DS - Rev C 2/12 EN
1.
©2009 Aptina Imaging Corporation All rights reserved.
http://www.Datasheet4U.com
1 page  
Aptina Confidential and Proprietary
MT9J003: 1/2.3-Inch 10Mp CMOS Digital Image Sensor
List of Figures
List of Figures
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Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
HiSPi Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
48-Pin iLCC Parallel Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Delaying the clock_lane with Respect to data_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Delaying data_lane with Respect to the clock_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Steaming vs. Packetized Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Pixel Data Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Row Timing and FV/LV Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Single READ From Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Single READ From Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Sequential READ, Start From Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Sequential READ, Start From Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Effect of Limiter on the Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Timing of Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MT9J003 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Sequence for Programming the MT9J003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Effect of Horizontal Mirror on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Effect of Vertical Flip on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Pixel Array Readout Without Subsampling and With 2x2 Skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Combinations of Pixel Skipping in the MT9J003 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Pixel Binning and Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Pixel Skipping Combined with Summing or Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
LED Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
LED Flash Enabled Following Forced Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Overview of Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Entering and Leaving a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Controlling the Reset and Integration Phases of the Global Reset Sequence . . . . . . . . . . . . . . . . . . . .53
Control of the Electromechanical Shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Controlling the SHUTTER Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Using FLASH With Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Global Reset Bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Entering Soft Standby During a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Test Cursor Behavior With Image Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Hard Standby and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Soft Standby and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Two-WIre Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
HiSPi Eye Diagram for Both Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
HiSPi Skew Between Data Signals Within the PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
48-Pin iLCC Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
48-Pin tPLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PDF: 4791388811 Source: 9166348326
MT9J003-DS - Rev C 2/12 EN
5.
©2009 Aptina Imaging Corporation. All rights reserved.
5 Page 
Aptina Confidential and Proprietary
MT9J003: 1/2.3-Inch 10Mp CMOS Digital Image Sensor
Signal Descriptions
Signal Descriptions
Table 3 provides signal descriptions for MT9J003 die. For pad location and aperture
information, refer to the MT9J003 die data sheet.
Table 3:
Signal Descriptions
Pad Name
EXTCLK
RESET_BAR
(XSHUTDOWN)
SCLK
GPI[3:0]
TEST
SDATA
LINE_VALID
FRAME_VALID
DOUT[11:0]
PIXCLK
FLASH
SHUTTER
VPP
VDD_TX0
VDD_SLVS
VDD_SLVS_TX
VAA
VAA_PIX
AGND
VDD
VDD_IO
DGND
VDD_PLL
GND_PLL
PIXGND
SLVS_0P
SLVS_0N
SLVS_1P
SLVS_1N
SLVS_2P
SLVS_2N
SLVS_3P
SLVS_3N
Pad Type
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Output
Output
Output
Output
Output
Output
Output
Output
Description
Master clock input, 6–48 MHz.
Asynchronous active LOW reset. When asserted, data output stops and all internal registers are
restored to their factory default settings.
Serial clock for access to control and status registers.
General purpose inputs. After reset, these pads are powered-down by default; this means that it is not
necessary to bond to these pads. Any of these pads can be configured to provide hardware control of
the standby, output enable, SADDR select, and shutter trigger functions.
Can be left floating if not used.
Enable manufacturing test modes. It should not be left floating. It can be tied to ground orVDD_IO
when used in parallel or HiSPi. It should be connected to DGND for normal operation of the CCP2
configured sensor, or connected to VDD_IO power for the MIPI®-configuredsensor.
Serial data from READs and WRITEs to control and status registers.
LINE_VALID (LV) output. Qualified by PIXCLK.
FRAME_VALID (FV) output. Qualified by PIXCLK.
Parallel pixel data output. Qualified by PIXCLK.
Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs.
Flash output. Synchronization pulse for external light source. Can be left floating if not used.
Control for external mechanical shutter. Can be left floating if not used.
Power supply used to program one-time programmable (OTP) memory. Disconnect pad when not
programming or when feature is not used.
PHY power supply. Digital power supply for the MIPI or CCP2 serial data interface. Aptina recommends
that VDD_TX0 is always tied to VDD when using an unpackaged sensor.
HiSPi power supply for data and clock output. This should be tied to VDD
Digital power supply for the HiSPi I/O.
Analog power supply.
Analog power supply for the pixel array.
Analog ground.
Digital power supply.
I/O power supply.
Common ground fordigital and I/O.
PLL power supply.
PLL ground.
Pixel ground.
Lane 1 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Lane 1 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
Lane 2 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Lane 2 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
Lane 3 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Lane 3 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
Lane 4 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Lane 4 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
PDF: 4791388811 Source: 9166348326
MT9J003-DS - Rev C 2/12 EN
11
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©2009 Aptina Imaging Corporation. All rights reserved.
11 Page | ||
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| PDF Descargar | [ Datasheet MT9J003.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT9J003 | 1/2.3-Inch 10Mp CMOS Digital Image Sensor | Aptina Imaging Corporation |
| MT9J003 | 1/2.3-Inch 10Mp CMOS Digital Image Sensor |  ON Semiconductor |
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