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What is 24C16?

This electronic component, produced by the manufacturer "FairchildSemiconductor", performs the same function as "16K-Bit Standard 2-Wire Bus Interface Serial EEPROM".


24C16 Datasheet PDF - FairchildSemiconductor

Part Number 24C16
Description 16K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Manufacturers FairchildSemiconductor 
Logo FairchildSemiconductor Logo 


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NM24C16/17 – 16K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
February 2000
General Description
The NM24C16/17 devices are 16,384 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 8Kbit) of the memory of the NM24C17 can be
write protected by connecting the WP pin to VCC. This section of
memory then becomes unalterable unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Block Diagram
VCC
VSS
WP
SDA
SCL
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER
CONTROL
LOGIC
Features
I Extended operating voltage 2.7V – 5.5V
I 400 KHz clock frequency (F) at 2.7V - 5.5V
I 200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I IIC compatible interface
– Provides bi-directional data transfer protocol
I Schmitt trigger inputs
I Sixteen byte page write mode
– Minimizes total write time per byte
I Self timed write cycle
Typical write cycle time of 6ms
I Hardware Write Protect for upper half (NM24C17 only)
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
H.V. GENERATION
TIMING &CONTROL
XDEC
E2PROM
ARRAY
WORD
ADDRESS
COUNTER
R/W YDEC
CK
DIN
DATA REGISTER
DOUT
© 1998 Fairchild Semiconductor Corporation
NM24C16/17 Rev. G
1
DS500072-1
www.fairchildsemi.com

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24C16 equivalent
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
VCC x 0.1 to VCC x 0.9
10 ns
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7
Output Load
1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC
0.1VCC
0.7VCC
0.3VCC
DS500072-6
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
Min Max
400 KHz
Min Max
fSCL SCL Clock Frequency
TI Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
100
400
50
tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9
tBUF Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
tHIGH
tSU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
tHD:DAT
Data in Hold Time
20
20
tSU:DAT
Data in Setup Time
250
100
tR SDA and SCL Rise Time
1 0.3
tF SDA and SCL Fall Time
300 300
tSU:STO
Stop Condition Setup Time
4.7
0.6
tDH Data Out Hold Time
300
50
tWR
(Note 3)
Write Cycle Time - NM24C16/17
- NM24C16/17L, NM24C16/17LZ
10
15
10
15
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C16/17 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
tF
tLOW
SCL
SDA
tSU:STA
tHD:STA
;;IN
SDA
OUT
tAA
tHIGH
tHD:DAT
tR
tLOW
tSU:DAT
tDH
tSU:STO
tBUF
DS500072-7
NM24C16/17 Rev. G
5 www.fairchildsemi.com


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1. 2-Wire Bus Interface Serial EEPROM

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