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PDF 24AA32A Data sheet ( Hoja de datos )
| Número de pieza | 24AA32A | |
| Descripción | 32K I2C Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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24AA32A/24LC32A
32K I2C™ Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA32A
1.7-5.5
400 kHz(1)
24LC32A 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V.
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation down to 1.7V for
24AA32A devices, 2.5V for 24LC32A devices
• Low-Power CMOS Technology:
- Active current 1 mA, typical
- Standby current 1 A, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection > 4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, SOIJ,
TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN,
5-lead SOT-23 and Chip Scale
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Types
PDIP/MSOP/SOIC/SOIJ/TSSOP
A0 1
8 VCC
X-Rotated TSSOP
(X/ST)
SCL
A1 2
A2 3
VSS 4
7 WP
WP 1
6
SCL
VCC
A0
2
3
5 SDA A1 4
8 SCL VSS
7 SDA
6
5
VSS
A2
SDA
Description:
The Microchip Technology Inc. 24AA32A/24LC32A
(24XX32A*) is a 32 Kbit Electrically Erasable PROM.
The device is organized as a single block of 4K x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 A and 1 mA,
respectively. It has been developed for advanced, low-
power applications such as personal communications
or data acquisition. The 24XX32A also has a page write
capability for up to 32 bytes of data. Functional address
lines allow up to eight devices on the same bus, for up
to 256 Kbits address space. The 24XX32A is available
in the standard 8-pin PDIP, surface mount SOIC, SOIJ,
TSSOP, DFN, TDFN and MSOP packages. The
24XX32A is also available in the 5-lead SOT-23 and
Chip Scale packages.
Block Diagram
A0 A1 A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O SCL
SDA
Vcc
VSS
YDEC
Sense Amp.
R/W Control
SOT-23
15
2
34
DFN/TDFN
CS (Chip Scale)(1)
WP A0 1
A1 2
A2 3
VCC VSS 4
8 VCC VCC 1
2 VSS
7 WP WP
6 SCL SCL
3
4 5 SDA
5 SDA
(Top Down View,
Balls Not Visible)
Note 1: Available in I-temp, “AA” only.
*24XX32A is used in this document as a generic part number for the 24AA32A/24LC32A devices.
2010 Microchip Technology Inc.
DS21713L-page 1
1 page  
24AA32A/24LC32A
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
PDIP
SOIC
SOIJ
TSSOP
Rotated
TSSOP
DFN(1)
TDFN(1)
MSOP SOT-23
CS
Description
A0 1 1 1
1
3
1
1
1 — — Chip Address Input
A1 2 2 2
2
4
2
2
2 — — Chip Address Input
A2 3 3 3
3
5
3
3
3 — — Chip Address Input
VSS 4 4 4
4
64
4
4 2 2 Ground
SDA 5 5 5
5
7
5
5
5 3 5 Serial Address/Data I/O
SCL 6 6 6
6
8
6
6
6 1 4 Serial Clock
WP 7 7 7
7
1
7
7
7 5 3 Write-Protect Input
VCC 8 8 8
8
28
8
8 4 1 +1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX32A for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 and chip scale
packages.
2.2 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz)
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
2010 Microchip Technology Inc.
DS21713L-page 5
5 Page 
24AA32A/24LC32A
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
control byte is set to ‘1’. There are three basic types of
read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX32A contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX32A issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX32A discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must
first be set. This is accomplished by sending the word
address to the 24XX32A as part of a write operation
(R/W bit set to ‘0’). Once the word address is sent, the
master generates a Start condition following the
acknowledge. This terminates the write operation, but
not before the internal Address Pointer is set. The
master issues the control byte again, but with the R/W
bit set to a ‘1’. The 24XX32A will then issue an
acknowledge and transmit the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition which causes the 24XX32A
to discontinue transmission (Figure 8-2). After a
random Read command, the internal address counter
will point to the address location following the one that
was just read.
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
SDA Line
S
Bus Activity
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX32A transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX32A to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX32A contains an internal Address
Pointer which is incremented by ‘1’ upon completion of
each operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The internal Address Pointer will automati-
cally roll over from address FFF to address 000 if the
master acknowledges the byte received from the array
address FFF.
Data (n)
A
C
K
S
T
O
P
P
N
O
A
C
K
2010 Microchip Technology Inc.
DS21713L-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24AA32A.PDF ] | |
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