24AA128 Datasheet PDF - MicrochipTechnology
| Part Number | 24AA128 | |
| Description | 128K I2C CMOS Serial EEPROM | |
| Manufacturers | MicrochipTechnology | |
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24AA128/24LC128/24FC128
128K I2C™ CMOS Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Automotive (E): -40C to +125C
24AA128 1.7-5.5V 400 kHz(1)
24LC128
24FC128
2.5-5.5V
1.7-5.5V
400 kHz
1 MHz(2)
Note 1: 100 kHz for VCC < 2.5V.
2: 400 kHz for VCC < 2.5V.
I
I, E
I
Features:
• Single Supply with Operation down to 1.7V for
24AA128/24FC128 devices, 2.5V for 24LC128
Devices
• Low-Power CMOS Technology:
- Write current 3 mA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 5 ms, typical
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP, and Chip Scale Packages
• Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial
Electrically Erasable PROM (EEPROM), capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device also has a page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads up to the 128K
boundary. Functional address lines allow up to eight
devices on the same bus, for up to 1 Mbit address
space. This device is available in the standard 8-pin
plastic DIP, SOIC (3.90 mm and 5.28 mm), TSSOP,
MSOP, DFN, TDFN and Chip Scale packages.
Block Diagram
A0 A1 A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
XDEC
EEPROM
Array
Page Latches
YDEC
VCC
VSS Sense Amp.
R/W Control
*24XX128 is used in this document as a generic part number
for the 24AA128/24LC128/24FC128 devices.
Package Types
PDIP/SOIC
TSSOP/MSOP1
DFN/TDFN
CS (Chip Scale)2
A0 1
A1 2
A2 3
VSS 4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Note 1: Pins A0 and A1 are no-connects for the MSOP package only.
2: Available in I-temp, “AA” only.
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
WP
VCC A1 A0
123
45
6 78
SDA SCL VSS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
A2
2010 Microchip Technology Inc.
DS21191S-page 1
|
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24AA128/24LC128/24FC128
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name PDIP SOIC TSSOP MSOP DFN(1) TDFN(1)
CS
Function
A0
A1
(NC)
A2
VSS
SDA
SCL
WP
VCC
Note 1:
1 1 1 — 1 1 3 User Configurable Chip Select
2 2 2 — 2 2 2 User Configurable Chip Select
— — — 1, 2 — — — Not Connected
3 3 3 3 3 3 5 User Configurable Chip Select
4 4 4 4 4 4 8 Ground
5 5 5 5 5 5 6 Serial Data
6 6 6 6 6 6 7 Serial Clock
7 7 7 7 7 7 4 Write-Protect Input
8 8 8 8 8 8 1 +1.7V to 5.5V (24AA128)
+2.5V to 5.5V (24LC128)
+1.7V to 5.5V (24FC128)
The exposed pad on the DFN/TDFN package can be connected to VSS or left floating.
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX128 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions while the
24XX128 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2010 Microchip Technology Inc.
DS21191S-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 24AA128 electronic component. |
| Information | Total 30 Pages | |
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| Download | [ 24AA128.PDF Datasheet ] | |
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