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PDF AK1546 Data sheet ( Hoja de datos )
| Número de pieza | AK1546 | |
| Descripción | 3GHz Low Noise Integer-N Frequency Synthesizer | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK1546]
AK1546
3GHz Low Noise Integer-N Frequency Synthesizer
1. Overview
The AK1546 is an Integer-N PLL (Phase Locked Loop) frequency synthesizer, covering a wide range of frequency
from 500MHz to 3GHz. Consisting of a highly accurate charge pump, a reference divider, a programmable divider
and a dual-modulus prescaler (P/P+1), this product provides high performance, very low Phase Noise and small
footprints.
An ideal PLL can be achieved by combining the AK1546 with the external loop filter and VCO (Voltage Controlled
Oscillator). Access to the registers is controlled via a 3-wire serial interface. The operating supply voltage is from
2.7V to 3.3V, and the charge pump circuit and the serial interface can be driven by individual supply voltage.
2. Features
Operating frequency :
Programmable charge pump current :
Fast lock mode for improved lock time :
Supply Voltage :
Separate Charge Pump Power Supply :
Excellent Phase Noise :
On-chip lock detection feature of PLL :
Digit
Package :
Operating temperature :
500MHz to 3GHz
647μA to 5176μA typical with 8steps
The current range can be controlled by an external resistor.
The programmable timer can switch two charge pump
current setting.
2.7 to 3.3 V (PVDD, AVDD pins)
PVDD to 5.5V (CPVDD pin)
-226dBc/Hz
Selectable P hase F requency D etector (P FD) Output o r
al filtered lock detect
20pin QFN (0.5mm pitch, 4mm×4mm×0.75mm)
-40°C to 85°C
MS1388-E-00 1
2012/3
http://www.Datasheet4U.com
1 page  
2. Pin Assignments
[AK1546]
20 19 18 17 16
CPVSS 1
15 LD
TEST1 2
AVSS 3
RFINN 4
TOP
VIEW
14 LE
13 DATA
12 CLK
RFINP 5
11 PDN
6 7 8 9 10
20pin QFN (0.5mm pitch, 4mm×4mm)
MS1388-E-00 5
2012/3
5 Page 
[AK1546]
8. Block Functional Descriptions
1. Frequency Setup
The following formula is used to calculate the frequency setting for the AK1546.
Frequency setting (external VCO output frequency) = FPFD × N
Where :
N
FPFD
P
B
A
: Dividing number N = [ (P × B) + A ]
: Phase detector frequency FPFD = [REFIN] pin input frequency / R counter dividing number
: Prescaler Value (See < Address2>:{Pre[1:0]})
: B (Programmable) counter value (See <Address1>:{B[12:0]})
: A (Swallow) counter value (See <Address1>:{A[5:0]})
Calculation example
The output frequency of external reference frequency oscillator is 10MHz, and FPFD is 200kHz and VCO
frequency is 2460MHz.
AK1546 setting :
R (Reference counter)=10000000/200000 = 50 (<Address0>:{R[13:0]}= “50”)
P=32 (<Address2>:{PRE[1:0]}=”10Bin”)
B=384 (<Address1>:{B[12:0]}=”384”)
A=12 (<Address1>:{A[5:0]}=”12”)
Frequency setting = 200kHz × [ (32×384) + 12] = 2460MHz
Lower limit for setting consecutive dividing numbers
In the AK1546, it is impossible to set consecutive dividing numbers below the lower limit. The lower limit is
calculated by the following formula;
Nmin=P2-P
For example, in the case of P=16, it can be set 240 and over as consecutive dividing numbers.
MS1388-E-00 11
2012/3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK1546.PDF ] | |
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