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PDF HM62V256LT-8SL Data sheet ( Hoja de datos )
| Número de pieza | HM62V256LT-8SL | |
| Descripción | 32768-word x 8-bit Low Voltage Operation CMOS Static RAM | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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HM62V256 Series
32,768-word × 8-bit Low Voltage Operation CMOS Static RAM
Features
• Low voltage operation SRAM
Operating Supply Voltage: 2.7 V to 3.6 V
• 0.8 µm Hi-CMOS process
• High speed
Access time: 70/85/100 ns (max)
• Low power
Standby: 0.15 µW (typ)
• Completely static memory
No clock or timing strobe required
• Directly LVTTL compatible: All inputs and outputs
ADE-203-136E (Z)
Rev. 5.0
Jun. 19, 1995
Ordering Information
Type No.
HM62V256LFP-10T
HM62V256LFP-7SLT
HM62V256LFP-10SLT
HM62V256LFP-8ULT
HM62V256LT-10
HM62V256LT-8SL
HM62V256LTM-10
HM62V256LTM-7SL
HM62V256LTM-10SL
HM62V256LTM-8UL
Access Time
100 ns
70 ns
100 ns
85 ns
100 ns
85 ns
100 ns
70 ns
100 ns
85 ns
Package
450 mil 280 pin plastic SOP (FP-28DA)
8 mm × 14 mm 32 pin TSOP (normal type) (TFP-32DA)
8 mm × 13.4 mm 28-pin TSOP (normal type) (TFP-28DA)
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1 page  
Function Table
WE CS
OE
XHX
HL H
HL L
LLH
LLL
Note: X: H or L
Mode
Not selected
Output disable
Read
Write
Write
VCC Current
ISB, ISB1
ICC
ICC
ICC
ICC
HM62V256 Series
I/O Pin
High-Z
High-Z
Dout
Din
Din
Ref. Cycle
—
—
Read cycle (1)–(3)
Write cycle (1)
Write cycle (2)
Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Terminal voltage*1
Power dissipation
Operating temperature
VCC
VT
PT
Topr
Storage temperature
Tstg
Storage temperature under bias
Tbias
Notes: 1. Relative to VSS
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 4.6V
Value
–0.5 to 4.6
–0.5*2 to VCC+0.5*3
1.0
0 to + 70
–55 to +125
–10 to +85
Unit
V
V
W
°C
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
VCC
VSS
Input high(logic 1) voltage
VIH
Input low(logic 0) voltage
VIL
Note: 1. VT min: –3.0 V for pulse half-width ≤ 50 ns
Min
2.7
0
0.7VCC
–0.3 *1
Typ
3.0
0
—
—
Max
3.6
0
VCC+0.3
0.2VCC
Unit
V
V
V
V
5
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5 Page 
Write Timing Waveform (2) (OE Low Fixed)
HM62V256 Series
Address
CS
WE
Dout
Din
t WC
Valid address
t CW
t WR
*1
t AW
tWP
tAS
tWHZ
High impedance
t OH
t OW
*2
*3
t DW tDH
Valid data
*4
Notes: 1. If CS goes low simultaneously with WE going low or after WE going low,
the outputs remain in the high impedance state.
2. Dout is the same phase of the write data of this write cycle.
3. Dout is the read data of next address.
4. If CS is low during this period, I/O pins are in the output state. Therefore, the input
signals of theopposite phase to the output must not be applied to them.
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HM62V256LT-8SL.PDF ] | |
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