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What is EN25Q32B?

This electronic component, produced by the manufacturer "Eon Silicon Solution", performs the same function as "32 Megabit Serial Flash Memory".


EN25Q32B Datasheet PDF - Eon Silicon Solution

Part Number EN25Q32B
Description 32 Megabit Serial Flash Memory
Manufacturers Eon Silicon Solution 
Logo Eon Silicon Solution Logo 


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EN25Q32B
EN25Q32B
32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
32 M-bit Serial Flash
- 32 M-bit/4096 K-byte/16384 pages
- 256 bytes per programmable page
Standard, Dual or Quad SPI
- Standard SPI: CLK, CS#, DI, DO, WP#
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
High performance
- 104MHz clock rate for one data bit
- 80MHz clock rate for two data bits
- 50MHz clock rate for four data bits
Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- 1024 sectors of 4-Kbyte
- 64 blocks of 64-Kbyte
- Any sector or block can be erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.3ms typical
- Sector erase time: 90ms typical
- Block erase time 500ms typical
- Chip erase time: 25 seconds typical
Lockable 512 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- 16 pins SOP 300mil body width
- 24 balls TFBGA (6x8mm)
- All Pb-free packages are RoHS compliant
Industrial temperature Range
GENERAL DESCRIPTION
The EN25Q32B is a 32 Megabit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q32B supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI),
DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz for Dual Output when using the Dual Output Fast Read instructions,
and SPI clock frequencies of up to 50MHz are supported allowing equivalent clock rates of 200MHz for
Quad Output when using the Quad Output Fast Read instructions. The memory can be programmed 1
to 256 bytes at a time, using the Page Program instruction.
The EN25Q32B is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25Q32B can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. D, Issue Date: 2011/07/07
www.eonssi.com
http://www.Datasheet4U.com

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EN25Q32B equivalent
Table 1. Pin Names
Symbol
CLK
DI (DQ0)
DO (DQ1)
CS#
WP# (DQ2)
NC(DQ3)
Vcc
Vss
NC
Pin Name
Serial Clock Input
Serial Data Input (Data Input Output 0) *1
Serial Data Output (Data Input Output 1) *1
Chip Enable
Write Protect (Data Input Output 2) *2
Not Connect (Data Input Output 3) *2
Supply Voltage (2.7-3.6V)
Ground
No Connect
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
EN25Q32B
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25Q32B support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. D, Issue Date: 2011/07/07
www.eonssi.com
http://www.Datasheet4U.com


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