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PDF BU9873 Data sheet ( Hoja de datos )
| Número de pieza | BU9873 | |
| Descripción | I2C BUS Serial Interface RTC | |
| Fabricantes | ROHM Semiconductor | |
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Datasheet
Real-Time Clock (RTC) series
I2C BUS Serial Interface RTC
with High-precision Oscillation Adjustment
BU9873
Outline
The BU9873 is a CMOS real-time clock, which has a
built-in interrupt generation function. This product is
connected to the CPU via I2C interface, and configured to
perform serial transmission of time and calendar data to
the CPU. A high-precision oscillation adjustment circuit is
also integrated, which is capable of adjusting time counts
with digital method, and correcting deviations in the
oscillation frequency of the crystal oscillator.
Important Characteristics
■ Time Keeping Voltage
■ Time Keeping Current 1
(VDD=3V, Ta=+25°C)
■ Time Keeping Current 2
(VDD=3V, Ta=-40°C to +85°C)
■ Power Supply Voltage
■ Access Frequency 1
(VDD=1.8V to 2.5V)
■ Access Frequency 2
(VDD=2.5V to 5.5V)
1.45V to 5.5V
0.4µA (Typ)
1.0µA (Max)
1.8V to 5.5V
100kHz (Max)
400kHz (Max)
Features
■ Connected to the CPU via I2C Interface
■ Time (Hour ･ Minute ･ Second, Selectable 12-Hour
and 24-Hour Mode Setting)
■ Calendar (Year･Month･Day･Week)
■ Periodic Interrupt Function
(Output from INTRB, Ranging from 1 Second to 1
Month)
■ Alarm Interrupt Function
(Day-of-Week ･ Hour ･ Minute in Setting Format,
Output from INTRB)
■ Oscillation Halt Sensing Function
■ 32.768 kHz Clock Output
(Output from 32KOUT with Control Pin)
■ ±30 Second Adjustment Function
■ Automatic Leap Year Recognition up to the Year
2099
■ Built-in Oscillation Stabilizing Capacitors (CG, CD)
■ High-Precision Oscillation Adjustment Circuit
Package
W (Typ) x D (Typ) x H (Max)
SOP8
MSOP8
5.00mm x 6.20mm x 1.71mm 2.90mm x 4.00mm x 0.90mm
SOP- J8
VSON008X2030
4.90mm x 6.00mm x 1.65mm 2.00mm x 3.00mm x 0.60mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
○Product structure: Silicon monolithic integrated circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/37
TSZ02201-0919AGZ00010-1-2
13.Sep.2013 REV.001
http://www.Datasheet4U.com
1 page  
BU9873
Datasheet
DC Characteristics
Item
“H” Input Voltage
Symbol
VIH
Pin Name
SCL, SDA
Spec
Unit
Min Typ Max
0.7VDD － VDD+0.3 V
Conditions
“L” Input Voltage
VIL
SCL, SDA
-0.3 － 0.3VDD V
“H” Output Current
IOH 32KOUT － － -0.5 mA VOH=VDD-0.5V
“L” Output Current
IOL1 INTRB, 32KOUT
IOL2 SDA
1
6
－ － mA
－ － mA
VOL1=0.4V
VOL2=0.4V
Input Leakage Current
IILK
SCL
-1 － 1 μA VIN=5.5V or VSS, VDD=5.5V
Output Off State Leakage
Current
IOZ
IDD1
SDA, INTRB,
32KOUT
VDD
-1 － 1 μA
－ 0.4 0.6 μA
Standby Current
(time keeping current)
IDD2
VDD
－ － 1.0 μA
IDD3 VDD － － 1.35 μA
Internal Oscillation
Capacitance 1
CG OSCIN － 10 －
Internal Oscillation
Capacitance 2
CD OSCOUT － 10 －
Unless otherwise specified: Vss=0V, VDD=3V, Topt=−40°C to +85°C, Oscillation frequency=32.768 kHz
(load capacitance CL=6pF, equivalent series resistance R1=20kΩ)
pF
pF
VOUT=5.5V or VSS,
VDD=5.5V
VDD=3V,
Topt=25°C,
SCL, SDA=3V,
CGOUT=CDOUT=0pF,
Output=Open(Note1)
VDD=3V,
Topt=-40°C to +85°C,
SCL, SDA=3V,
CGOUT=CDOUT=0pF,
Output=Open(Note1)
VDD=5.5V,
Topt=-40°C to +85°C,
SCL, SDA=5.5V,
CGOUT=CDOUT=0pF,
Output=Open(Note1)
(Note 1) In this mode, 32KOUT is disabled and no clock is output from this pin.
For time keeping current when outputting 32-kHz pulse from 32KOUT pin (this pin without loading), please refer to “P.7 Typical Performance Curves”.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/37
TSZ02201-0919AGZ00010-1-2
13.Sep.2013 REV.001
http://www.Datasheet4U.com
5 Page 
BU9873
Datasheet
1. Communication Interface
This product can read/write data from I2C bus interface with 2-wires: SDA (data) and SCL (clock). Since the output of SDA
pin is open-drain, data transferring between CPU with different supply voltage is possible by adopting a pull-up resistor on
the circuit board.
1-1. I2C BUS Communication
I2C BUS data communication starts by a start condition input, and ends by a stop condition input. The data length is 8-bit,
and acknowledges signal is always required after each byte.
I2C BUS carries out data transmission between plural devices connected by 2-wires: serial data (SDA) and serial clock
(SCL). Among these devices, there is “master” that generates clock and control the start and end signal, and “slave” that is
controlled by unique device address. RTC is “slave”. And the device that outputs data to bus during data transferring is
called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7 8 9
SCL
S
START ADDRESS
condition
R/W
ACK
1-7 8 9
DATA
ACK
1-7 8 9
DATA
P
ACK STOP
condition
Figure 17. I2C BUS communication
1-2. Start Condition (start bit recognition)
Before executing any command, start condition (start bit) is necessary, where SDA goes from “H” down to “L” when
SCL is “H”.
This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, no command will be executed.
1-3. Stop Condition (stop bit recognition)
Every command can be ended by stop condition (stop bit), where SDA rising from “L” to “H” when SCL is “H”.
1-4. Acknowledge (ACK) Signal
・This acknowledge (ACK) signal is a software rule to judge whether data transfer has been executed successfully or not. For
master and slave, the device (µ-COM during inputting slave address of write command, read command, and this IC during
outputting data of read command) at the transmitter side releases the bus after outputting 8-bit data.
・The device (this IC during inputting slave address of write command, read command, and µ-COM during outputting data of
read command) at the receiver side sets SDA “L” during the ninth clock cycle, and outputs acknowledge signal (ACK)
showing that it has received the 8-bit data.
・This IC outputs acknowledge signal (ACK) “L” after recognizing start condition and 8-bit slave address.
・Every write action outputs acknowledge signal (ACK) “L” after receiving 8-bit data (word address and write data).
・Every read action outputs 8-bit data (read data), and detects acknowledge signal (ACK) “L”. When acknowledge signal
(ACK) is detected, and stop condition is not sent from the master (µ-COM) side, this IC will continue to output data. When
acknowledge signal (ACK) is not detected, this IC will stop data transfer, and end read action after recognizing stop
condition (stop bit). Then, this IC will get in off-status.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/37
TSZ02201-0919AGZ00010-1-2
13.Sep.2013 REV.001
http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet BU9873.PDF ] | |
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