NP8P128A13B1760E Datasheet PDF - Micron
| Part Number | NP8P128A13B1760E | |
| Description | P8P Parallel Phase Change Memory | |
| Manufacturers | Micron | |
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P8P Parallel Phase Change
Memory (PCM)
128Mb: P8P Parallel PCM
Features
Features
• High-performance READ
– 115ns initial READ access
– 135ns initial READ access
– 25ns, 8-word asynchronous-page READ
• Architecture
– Asymmetrically blocked architecture
– Four 32KB parameter blocks with top or bottom
configuration
– 128KB main blocks
– Serial peripheral interface (SPI) to enable lower
pin count on-board programming
• Phase change memory (PCM)
– Chalcogenide phase change storage element
– Bit-alterable WRITE operation
• Voltage and power
– VCC (core) voltage: 2.7–3.6V
– VCCQ (I/O) voltage: 1.7–3.6V
– Standby current: 80µA (TYP)
• Quality and reliability
– More than 1,000,000 WRITE cycles
– 90nm PCM technology
• Temperature
– Commercial: 0°C to +70°C (115ns initial READ
access)
– Industrial: –40°C to +85°C (135ns initial READ
access)
• Simplified software management
– No block erase or cleanup required
– Bit twiddle in either direction (1:0, 0:1)
– 35µs (TYP) PROGRAM SUSPEND
– 35µs (TYP) ERASE SUSPEND
– Flash data integrator optimized
– Scalable command set and extended command set
compatible
– Common Flash interface capable
• Density and packaging
– 128Mb density
– 56-lead TSOP package
– 64-ball easy BGA package
• Security
– One-time programmable registers
64 unique factory device identifier bits
2112 user-programmable OTP bits
– Selectable OTP space in main array
– Three adjacent main blocks available for boot code
or other secure information
– Absolute WRITE protection: VPP = VSS
– Power transition ERASE/PROGRAM lockout
– Individual zero-latency block locking
– Individual block lock-down
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcm_1.fm - Rev. K 7/12 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Free Datasheet http://www.Datasheet4U.com
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128Mb: P8P Parallel PCM
List of Tables
List of Tables
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Top Parameter Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bottom Parameter Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
TSOP Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Easy BGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Command Codes and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Command Sequences in x16 Bus Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Read Identifier Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Buffered Programming and Bit-Alterable Buffer Write Timing Requirements . . . . . . . . . . . . . . . . . . .25
Bit Alterability vs. Flash Bit-Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Block Locking Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Locking State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Selectable OTP Block Locking Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Selectable OTP Block Locking Programming of PR-LOCK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Status Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2K OTP Space Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Power and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DC Current Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DC Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Test Configuration Component Value for Worst-Case Speed Conditions . . . . . . . . . . . . . . . . . . . . . . .53
Capacitance: TA = 25°C, f = 1 MHz1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Read Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Write Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
SPI AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Program and Erase Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Active Line Item Ordering Table (0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Active Line Item Ordering Table (–40°C to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Full WRITE STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
WRITE SUSPEND/RESUME Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure. . . . . . . . . . . . . . . . . . . . . . . . . .66
BLOCK ERASE Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
BLOCK ERASE FULL ERASE STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ERASE SUSPEND/RESUME Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
LOCKING OPERATIONS Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PROGRAM PROTECTION REGISTER Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
FULL STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Summary of Query Structure Output as a Function of Device and Model . . . . . . . . . . . . . . . . . . . . . .77
Example of Query Structure Output of x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Query Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcmLOT.fm - Rev. K 7/12 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com
Preview 5 Page |
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