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PDF AR8035 Data sheet ( Hoja de datos )
| Número de pieza | AR8035 | |
| Descripción | Integrated 10/100/1000 Gigabit Ethernet Transceiver | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
March 2012
Ver. 2.1
AR8035 Integrated 10/100/1000 Mbps Ethernet
Transceiver
General Description
The AR8035 is part of the Arctic family of
devices - which includes the AR8031, AR8033,
and the AR8035. It is Atheros’ 4th generation,
single port 10/100/1000 Mbps Tri-speed
Ethernet PHY. It supports RGMII interface to
the MAC.™
The AR8035 provides a low power, low BOM
(Bill of Materials) cost solution for
comprehensive applications including
consumer, enterprise, carrier and home
networks such as PC, HDTV, Gaming
machines, Blue-ray players, IPTV STB, Media
Players, IP Cameras, NAS, Printers, Digital
Photo Frames, MoCA/Homeplug
(Powerline)/EoC/ adapters and Home Router
& Gateways, etc.
The AR8035 integrates Atheros latest Green
Ethos® power saving technologies and
significantly saves power not only during work
time, but also during overtime. Atheros Green
Ethos® power savings include ultra-low power
in cable unplugged mode or port power down
mode, and automatic optimized power saving
based on cable length. Furthermore, the
AR8035 supports Wake-on-LAN (WoL) feature
to be able to help manage and regulate total
system power requirements.
The AR8035 embeds CDT (Cable Diagnostics
Test) technology on-chip which allows
customers to measure cable length, detect the
cable status, and identify remote and local PHY
malfunctions, bad or marginal patch cord
segments or connectors. Some of the possible
problems that can be detected include opens,
shorts, cable impedance mismatch, bad
connectors, termination mismatch, and a bad
transformer.
The AR8035 also integrates a voltage regulator
on chip. It reduces the termination R/C
circuitry on both the MAC interface (RGMII)
and line side.
The AR8035 supports IEEE 802.3az Energy
Efficient Ethernet (EEE) standard and Atheros
proprietary SmartEEE, which allows legacy
MAC/SoC devices without 802.3az support to
function as the complete 802.3az system. The
key features supported by the device are:
n 10BASE-Te PHY supports reduced transmit
amplitude.
n 100BASE-TX and 1000BASE-T use Low
Power Idle (LPI) mode to turn off unused
analog and digital blocks to save power
while data traffic is in idle.
Features
n 10BASE-Te/100BASE-TX/1000 BASE-T
IEEE 802.3 compliant
n Supports 1000 BASE-T PCS and auto-
negotiation with next page support
n Supports RGMII interface to MAC devices
with a broad I/O voltage level options
including 2.5V, 1.8V and 1.5V, and is
compatible with 3.3V I/O
n RGMII timing modes support internal delay
and external delay on Rx path
n Error-free operation up to 140 meters of
CAT5 cable
n Supports Atheros latest Green Ethos®
power saving modes with internal
automatic DSP power saving scheme
n Supports 802.3az (Energy Efficient Ethernet)
n Fully integrated digital adaptive equalizers,
echo cancellers, and near end crosstalk
(NEXT) cancellers
n Supports Wake-on-LAN (WoL) to detect
magic packet and notify the sleeping system
to wake up
n A robust Cable Discharge Event (CDE)
tolerance of ± 6kV
n A robust surge protection with ±750V/
differential mode and ±4KV/common
mode
n Jumbo Frame support up to 10KB (full
duplex)
n All digital baseline wander correction
n Automatic channel swap (ACS)
n Automatic MDI/MDIX crossover
n Automatic polarity correction
n IEEE 802.3u compliant Auto-Negotiation
n Software programmable LED modes
n Multiple Loopback modes for diagnostics
© 2011–2012 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New
Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®,
U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain
Technology™, Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications,
Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without
COMPANY CONFIDENTIAL
•1
Free Datasheet http://www.Datasheet4U.com
1 page  
Table of Contents
General Description ........................................ 1
Features ............................................................ 1
AR8035 Functional Block Diagram .............. 2
Revision History ............................................. 3
Table of Contents ............................................ 5
1 Pin Descriptions ............................ 7
2 Functional Description ............... 13
2.1 Transmit Functions ................................ 14
2.2 Receive Functions .................................. 14
2.2.1 Decoder Modes ........................... 14
2.2.2 Analog to Digital Converter ...... 14
2.2.3 Echo Canceller ............................. 14
2.2.4 NEXT Canceller .......................... 14
2.2.5 Baseline Wander Canceller ....... 14
2.2.6 Digital Adaptive Equalizer ....... 14
2.2.7 Auto-Negotiation ........................ 15
2.2.8 Smartspeed Function ................. 15
2.2.9 Automatic MDI/MDIX Crossover
15
2.2.10 Polarity Correction ..................... 15
2.3 Loopback Modes .................................... 15
2.3.1 Digital Loopback ......................... 15
2.3.2 External Cable Loopback ........... 15
2.3.3 Remote PHY Loopback .............. 16
2.4 Cable Diagnostic Test ............................ 16
2.5 LED Interface .......................................... 16
2.6 Power Supplies ....................................... 18
2.7 Management Interface .......................... 19
2.8 Atheros Green Ethos® .......................... 20
2.8.1 Low Power Modes ...................... 20
2.8.2 Shorter Cable Power Mode ....... 20
2.8.3 Hibernation Mode ...................... 20
2.9 IEEE 802.3az and Energy Efficient
Ethernet 21
2.9.1 IEEE 802.3az LPI Mode .............. 21
2.10 Atheros SmartEEE ................................ 22
2.11 Wake On LAN (WoL) ........................... 22
3 Electrical Characteristics ............ 23
3.1 Absolute Maximum Ratings ................ 23
3.2 Recommended Operating Conditions 23
3.3 RGMII Characteristics ........................... 24
3.4 MDIO Characteristics ............................ 26
3.5 XTAL/OSC Characteristics .................. 27
3.6 Power Pin Consumption ...................... 28
3.7 Typical Power Consumption Parameters
29
3.8 Power-on Sequence, Reset and Clock . 30
3.8.1 Power-on Sequence .................... 30
3.8.2 Reset and Clock Timing ............. 30
4 Register Descriptions ..................31
4.1 Register Summary ................................. 31
4.1.1 Control ......................................... 32
4.1.2 Status ............................................ 34
4.1.3 PHY Identifier [18:3] .................. 35
4.1.4 PHY Identifier [19:24] ................ 35
4.1.5 Auto-Negotiation Advertisement
35
4.1.6 Link Partner Ability (Base Page) 37
4.1.7 Auto-Negotiation Expansion .... 38
4.1.8 Next Page Transmit .................... 38
4.1.9 Link Partner Next Page ............. 39
4.1.10 1000 BASE-T Control ................. 39
4.1.11 1000 BASE-T Status .................... 41
4.1.12 MMD Access Address Register 42
4.1.13 MMD Access Control Register . 42
4.1.14 Extended Status .......................... 43
4.1.15 Function Control ......................... 43
4.1.16 PHY-Specific Status .................... 44
4.1.17 Interrupt Enable .......................... 45
4.1.18 Interrupt Status ........................... 46
4.1.19 Smart Speed ................................. 47
4.1.20 Cable Diagnostic Tester Control 47
4.1.21 LED Control ................................ 48
4.1.22 Cable Defect Tester Status ......... 49
4.1.23 Debug Port Address Offset ....... 49
4.1.24 Debug Port Data ......................... 49
4.2 Debug Register Descriptions ............... 50
4.2.1 RGMII RX Clock Delay Control 50
4.2.2 RGMII TX Clock Delay Control 50
4.2.3 Hibernation Control and RGMII
GTX Clock Delay Register ......... 51
4.2.4 100BASE-TX Test Mode Select . 52
4.2.5 1000BT external loopback
configure ...................................... 52
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • 5
November 2011 • 5
Free Datasheet http://www.Datasheet4U.com
5 Page 
Table 1-4.
PHY Pin
RXD0
RXD1
LED_ACT
RX_DV
RXD2
LED_1000
RXD3
RX_CLK
PHY Core
Configuration Signal Description
PHYADDRESS0
PHYADDRESS1
PHYADDRESS2
MODE0
MODE1
MODE2
MODE3
1.8V/1.5V
LED_ACT, RXD[1:0] sets the lower three bits of
the physical address. The upper two bits of the
physical address are set to the default, “00”
mode select bit 0
mode select bit 1
mode select bit 2
mode select bit 3
Select the RGMII/RMII I/O voltage level
1: 1.8V I/O
0: 1.5V I/O
Default
Internal
Weak Pull-
up/Pull-
down
0
0
1
0
0
1
0
0
NOTE: 0=Pull-down, 1=Pull-up
NOTE: Power on strapping pins are latched
during power-up reset or warm hardware reset.
NOTE: Some MAC devices input pins may drive
high/low during power-up or reset. So PHY
power on strapping status may be affected by
the MAC side. In this case an external 10kΩ pull-
down or pull-high resistor is needed to ensure a
stable expected status.
NOTE: When using 2.5V RGMII I/O voltage level,
RX_CLK can be pull-up or pull-down.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • 11
November 2011 • 11
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 66 Páginas | |
| PDF Descargar | [ Datasheet AR8035.PDF ] | |
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