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What is STM8S105C6?

This electronic component, produced by the manufacturer "STMicroelectronics", performs the same function as "16 MHz STM8S 8-bit MCU".


STM8S105C6 Datasheet PDF - STMicroelectronics

Part Number STM8S105C6
Description 16 MHz STM8S 8-bit MCU
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 


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STM8S105C4/6 STM8S105K4/6
STM8S105S4/6
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash,
integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C
Datasheet - production data
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: up to 32 Kbyte Flash; data
retention 20 years at 55 °C after 10 kcycle
Data memory: up to 1 Kbyte true data
EEPROM; endurance 300 kcycle
RAM: up to 2 Kbyte
Clock, reset and supply management
2.95 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
Clock security system with clock monitor
Power management:
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
Permanently active, low-consumption power-
on and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 37 external interrupts on 6 vectors
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
LQFP48 (7x7 mm) LQFP44 (10x10 mm) LQFP32 (7x7 mm)

UFQFPN32 (5x5 mm)

SDIP32 400ml
2x16-bit general purpose timer, with 2+3
CAPCOM channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Window watchdog and independent watchdog
timers
Communication interfaces
UART with clock output for synchronous
operation, SmartCard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I2C interface up to 400 kbit/s
Analog to digital converter (ADC)
10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
I/Os
Up to 38 I/Os on a 48-pin package including
16 high sink outputs
Highly robust I/O design, immune against
current injection
Unique ID
96-bit unique key for each device
September 2015
This is information on a product in full production.
DocID14771 Rev 15
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www.st.com

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STM8S105C6 equivalent
STM8S105x4/6
List of tables
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Table 48.
STM8S105x4/6 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviations for pin description tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S105x4/6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash, data EEPROM and RAM boundary address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Alternate function remapping bits [7:0] of OPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 57
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 58
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 59
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 61
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy with RAIN< 10 k, VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC accuracy with RAIN< 10 k, VDDA = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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