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PDF BM320240A Data sheet ( Hoja de datos )
| Número de pieza | BM320240A | |
| Descripción | LCD Module | |
| Fabricantes | EASTRISING | |
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Confidential Document
EASTRISING CORPORATION
LCD Module Specification
ITEM NO : BM320240A
R&D Dept.
Q.C. Dept.
Eng. Dept.
Prod. Dept.
Version:
Issued Date:
2004/11/18
Sheet Code:
Total Pages:
Free
1 page  
LCD MODULE
BM320240A Series
Version:1.0
z System bus READ/WRITE timing II (6800 )
tCYC6
E
R/W
tAW6
tEW
A0,CS
tAH6
D0∼D7
(WRITE)
D0∼D7
(READ)
tDS6
tACC6
tDH6
tOH6
Signal Symbol
Parameter
A0, CS
R/W
D0 to D7
E
tAH6
tAW6
tCYC6
tCC
tDS6
tDH6
tACC6
tOH6
tEW
Address hold time
Address setup time
System cycle time
Strobe pulsewidth
Data setup time
Data hold time
RD access time
Output disable time
Enable pulse width
Rating
min max
10 ---
30 ---
(1) ---
220 ---
120 ---
10 ---
--- 120
10 50
220 ---
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL = 100+1TTL
pF
Note: (1) t CYC6 = 2t C + t EW + t CEA + 75 > t ACV + 245:
memory control/movement control commands:
= 4tC + tEW + 30:
all other commands:
1. tCYC6 means a cycle of (CS.E) not E alone.
2.
z Display memory READ timing
EXTφO
tC
VCE
tW
tCE
tCYR
VA0∼VA15
VR/W
VD0∼VD7
tAS
tRCS
tCEA
tACY
tAHC
tW
tRCH
tCE3
tOH2
Signal Symbol
Parameter
EXT ∅0
tC Clock cycle
VCE
tW VCE high level pulse width
tCE VCE low level pulse width
VA0 tCYR Read cycle time
to VA15 tASC VCE address setup time (fall)
tAHC VCE address hold time (fall)
VR/W
tRCS VCE read cycle setup time (fall)
tRCH VCE read cycle hold time (fall)
tACV Address access time
VD0 tCEA VCE access time
to VD7
tOH2 Output data hold time
tCE2 VCE data off time
Note: 1. tCYR = 3tC
2. t ACV = 3t C –120
3. t CEA = 2t C –120
Rating
min max
100 ---
tc-40 ---
2tc-40 ---
(1) ---
tc-45 ---
2tc-40 ---
tc-45 ---
tc/2-35
--- (2)
--- (3)
0 ---
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL = 100pF
+1TTL
4 o f 34
Nov 18 2004
Free Datasheet http://www.Datasheet4U.com
5 Page 
LCD MODULE
BM320240A Series
(2) Above and below two-panel display
EL
EL
Y driver
X driver
X driver
Upper Panel
Lower Panel
Version:1.0
Nov 18 2004
X driver
X driver
(3) Left and right two-panel display
EI
YD
X driver
X driver
X driver
X driver
Y driver
Left Panel
Right Panel
1.6 IV
Screen origin compensation for inverse display. IV is usually set to 1.The best way of displaying inverted
characters is to Exclusive-OR the text layer with the graphics back-ground layer. However, inverted
characters at the top or left of the screen are difficult to read as the charac-ter origin is at the top-left of its
bitmap and there are no background pixels either above or to the left of these characters.The IV flag causes
the SED1330F to offset the text screen against the graphics back layer by one vertical pixel. Use the
horizontal pixel scroll function (HDOT SCR) to shift the text screen 1 to 7 pixels to the right. All characters
will then have the necessary surrounding background pixels that en-sure easy reading of the inverted
characters.
IV = 0: Screen top-line correction
IV = 1: No screen top-line correction (no offset)
Display start point
Back layer
IV
1 dot
HDOT SCR
Character
Dots 1 to 7
1.7 T/L
Selects TV or LCD mode. When TV mode is selected,the TV sync generator circuit is ON.
T/L = 0: LCD mode
T/L = 1: TV mode
1.8 DR
Selects output of an additional shift-clock cycle for every 64 pixels. The extra cycles are required for correct
operation of the enable chain when using a two-panel display.
DR = 0: Normal operation
DR = 1: Additional shift-clock cycles
1.9 FX
Sets the width, in pixels, of the character field. The character width in pixels is equal to FX + 1, where FX
can range from 00 to 07H inclusive. If data bit 3 is set (FX is in the range 08 to 0FH) and an 8-pixel font is
used, a space is inserted between characters. Note that the maximum character width in TV mode is eight
10 o f 34
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
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