PDF A25L512 Data sheet ( Hoja de datos )

Número de pieza	A25L512
Descripción	(A25L010 - A25L512) Serial Flash Memory
Fabricantes	AMIC
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No Preview Available ! A25L020/A25L010/A25L512 Series 2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors Document Title 2Mbit /1Mbit /512Kbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors Revision History Rev. No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 History Initial issue Add 8-pin TSSOP package type Add the spec. of ICC3 for 33MHz Modify DC/AC Characteristics Modify AC Characteristics Add packing description in Part Numbering Scheme P30: Change Data Retention and Endurance value from Max. to Min. P37: Add A25L512V-UF, A25L010V-UF and A25L020V-UF in the ordering information Add 8-pin USON (23mm) package type P33: Modify the fR to 66MHz (Max.) Add 8-pin WSON (65mm) package type P31 : Add the typical ICC3 @ 100Mhz / 50Mhz / 33Mhz Add typical ICC4 P28, 29 : Update power-up and power-down timing waveform P31: Modify DC Characteristics Issue Date February 27, 2008 September 2, 2008 January 9, 2009 April 21, 2009 April 30, 2010 October 20, 2010 December 23, 2010 January 31, 2011 October 28, 2011 March 30, 2012 May 9, 2012 Remark Final (May, 2012, Version 2.0) AMIC Technology Corp. Free Datasheet http://www.Datasheet4U.com 1 page SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the A25L020/A25L010/A25L512 Series falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1) Figure 1. Bus Master and Memory Devices on the SPI Bus SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDO SDI SCK Bus Master (ST6, ST7, ST9, ST10, Other) CS3 CS2 CS1 C DO DIO SPI Memory Device S W HOLD C DO DIO C DO DIO SPI Memory Device S W HOLD SPI Memory Device S W HOLD Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate. Figure 2. SPI Modes Supported CPOL CPHA 00 C 11 C DIO DO MSB MSB (May, 2012, Version 2.0) 4 AMIC Technology Corp. Free Datasheet http://www.Datasheet4U.com 5 Page A25L020/A25L010/A25L512 Series INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DIO) is sampled on the first rising edge of Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DIO), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, Read Device Identification and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select ( S ) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select ( S ) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select ( S ) must driven High when the number of clock pulses after Chip Select ( S ) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 5. Instruction Set Instruction Description WREN WRDI RDSR WRSR READ FAST_READ FAST_READ_DUAL _OUTPUT FAST_READ_DUAL _INPUT-OUTPUT PP SE BE CE DP RDID REMS RES Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes Read Data Bytes at Higher Speed Read Data Bytes at Higher Speed by Dual Output (1) Read Data Bytes at Higher Speed by Dual Input and Dual Output (1) Page Program Sector Erase Block Erase Chip Erase Deep Power-down Read Device Identification Read Electronic Manufacturer & Device Identification Release from Deep Power-down, and Read Electronic Signature Release from Deep Power-down One-byte Instruction Code 0000 0110 06h 0000 0100 04h 0000 0101 05h 0000 0001 01h 0000 0011 03h 0000 1011 0Bh 00111011 3Bh 10111011 0000 0010 0010 0000 1101 1000 1100 0111 1011 1001 1001 1111 1001 0000 BBh 02h 20h D8h C7h B9h 9Fh 90h 1010 1011 ABh Address Bytes 0 0 0 0 3 3 3 3(2) 3 3 3 0 0 0 1(3) 0 0 Note: (1) DIO = (D6, D4, D2, D0) DO = (D7, D5, D3, D1) (2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0) DO = (A23, A21, A19, …….., A7, A5, A3, A1) (3) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first Dummy Bytes 0 0 0 0 0 1 1 1(2) 0 0 0 0 0 0 2 3 0 Data Bytes 0 0 1 to ∞ 1 1 to ∞ 1 to ∞ 1 to ∞ 1 to ∞ 1 to 256 0 0 0 0 1 to ∞ 1 to ∞ 1 to ∞ 0 (May, 2012, Version 2.0) 10 AMIC Technology Corp. Free Datasheet http://www.Datasheet4U.com 11 Page

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