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PDF AR9271 Data sheet ( Hoja de datos )
| Número de pieza | AR9271 | |
| Descripción | Single-Chip 1x1 MAC/BB/Radio/PA/LNA | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
November 2011
AR9271 Single-Chip 1x1 MAC/BB/Radio/PA/LNA with USB
Interface for 802.11n 2.4 GHz WLANs
General Description
The Atheros AR9271 is a highly integrated single-
chip solution for 2.4 GHz 802.11n-ready wireless
local area networks (WLANs) that enables a high-
performance 1x1 configuration for wireless station
applications demanding robust link quality and
maximum throughput and range. The AR9271
integrates a multi-protocol MAC, baseband
processor, analog-to-digital and digital-to-analog
(ADC/DAC) converters, 1x1 radio transceiver, RF
switch, and USB interface in an all-CMOS device
for low power and small form factor applications.
The AR9271 implements half-duplex OFDM,
CCK, and DSSS baseband processing, supporting
72.2 Mbps for 20 MHz and 150 Mbps for 40 MHz
channel and IEEE 802.11b/g data rates. Other
features include signal detection, automatic gain
control, frequency offset estimation, symbol
timing, and channel estimation. The AR9271 MAC
supports the 802.11 wireless MAC protocol,
802.11i security, receive and transmit filtering,
error recovery, and quality of service (QoS).
The AR9271 supports one transmit traffic stream
and one receive traffic stream using one
integrated Tx chain and one receive chain for high
throughput and range performance. The Tx chain
combines baseband in-phase (I) and quadrature
(Q) signals, converts them to the desired
frequency, and drives the RF signal to the
antenna. The frequency synthesizer supports
frequencies defined by IEEE 802.11b/g/n
specifications.
The AR9271 supports frame data transfer to and
from the host using a USB interface that provides
interrupt generation/reporting, power save, and
status reporting. Other external interfaces include
serial EEPROM and GPIOs. The AR9271 is
interoperable with standard legacy 802.11b/g
devices.
Features
■ All-CMOS solution interoperable with IEEE
802.11b/g/n WLANs
■ Intergrated RF front end with high-output PA,
LNA, Rx/Tx switch
■ Internal diversity switch which selects antenna
1 or 2 for baseband signal processing
■ Supports optional external LNA, PA
■ 2.4 GHz WLAN MAC/BB processing
■ BPSK, QPSK, 16 QAM, 64 QAM, DBPSK,
DQPSK, and CCK modulation schemes
■ Supports 72.2 Mbps for 20 MHz and 150 Mbps
for 40 MHz channel operations
■ Wireless multimedia enhancements quality of
service support (QoS)
■ 802.11e-compatible bursting
■ Support for IEEE 802.11e and IEEE 802.11i
standards
■ WEP, TKIP, and AES hardware encryption
■ Reduced (short) guard interval
■ Frame aggregation
■ Block ACK
■ USB 2.0 interface
■ Supports the access of a serial peripheral (SPI)
compatible Flash memory, which includes
booting from an SPI Flash and auto-
installation
■ IEEE 1149.1 standard test access port and
boundary scan architecture supported
■ 68-pin, 8 mm x 8 mm LPCC package
AR9271 System Block Diagram
© 2010-11 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New
Wires®, Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®,
U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain
Technology™, Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications,
Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without
COMPANY CONFIDENTIAL
•1
Free Datasheet http://www.Datasheet4U.com
1 page  
6.5.8 Tx Configuration (TXCFG) ........ 61
6.5.9 Rx Configuration (RXCFG) ....... 62
6.5.10 MIB Control (MIBC) ................... 62
6.5.11 Timeout Prescale (TOPS) ........... 62
6.5.12 Rx No Frame (RXNF) ................. 63
6.5.13 Tx No Frame (TXNF) ................. 63
6.5.14 Rx Frame Gap Timeout (RFGTO)
63
6.5.15 Rx Frame Count Limit (RFCNT) 63
6.5.16 Global Tx Timeout (GTT) .......... 64
6.5.17 Global Tx Timeout Mode (GTTM)
64
6.5.18 Carrier Sense Timeout (CST) .... 64
6.5.19 Primary Interrupt Status (ISR_P) 65
6.5.20 Secondary Interrupt Status 0
(ISR_S0) ........................................ 67
6.5.21 Secondary Interrupt Status 1
(ISR_S1) ........................................ 67
6.5.22 Secondary Interrupt Status 2
(ISR_S2) ........................................ 68
6.5.23 Secondary Interrupt Status 3
(ISR_S3) ........................................ 68
6.5.24 Secondary Interrupt Status 4
(ISR_S4) ........................................ 69
6.5.25 Secondary Interrupt Status 5
(ISR_S5) ........................................ 69
6.5.26 Primary Interrupt Mask (IMR_P) 70
6.5.27 Secondary Interrupt Mask 0
(IMR_S0) ...................................... 71
6.5.28 Secondary Interrupt Mask 1
(IMR_S1) ...................................... 71
6.5.29 Secondary Interrupt Mask 2
(IMR_S2) ...................................... 72
6.5.30 Secondary Interrupt Mask 3
(IMR_S3) ...................................... 72
6.5.31 Secondary Interrupt Mask 4
(IMR_S4) ...................................... 73
6.5.32 Secondary Interrupt Mask 5
(IMR_S5) ...................................... 73
6.5.33 Primary Interrupt Status Read and
Clear (ISR_P_RAC) ..................... 74
6.5.34 Secondary Interrupt Status 0
(ISR_S0_S) .................................... 74
6.5.35 Secondary Interrupt Status 1
(ISR_S1_S) .................................... 74
6.5.36 Secondary Interrupt Status 2
(ISR_S2_S) .................................... 74
6.5.37 Secondary Interrupt Status 3
(ISR_S3_S) .................................... 74
6.5.38 Secondary Interrupt Status 4
(ISR_S4_S) .................................... 75
6.5.39 Secondary Interrupt Status 5
(ISR_S5_S) .................................... 75
6.6 QCU Registers ........................................ 76
Beacon Handling 76
6.6.1 Tx Queue Descriptor (Q_TXDP) 77
6.6.2 Tx Queue Enable (Q_TXE) ........ 78
6.6.3 Tx Queue Disable (Q_TXD) ...... 78
6.6.4 CBR Configuration (Q_CBRCFG)
78
6.6.5 ReadyTime Configuration
(Q_RDYTIMECFG) .................... 79
6.6.6 OneShotArm Set Control
(Q_ONESHOTARM_SC) ........... 79
6.6.7 OneShotArm Clear Control
(Q_ONESHOTARM_CC) .......... 79
6.6.8 Misc. QCU Settings (Q_MISC) . 80
6.6.9 Misc. QCU Status (Q_STS) ........ 82
6.6.10 ReadyTimeShutdown Status
(Q_RDYTIMESHDN) ................. 82
6.7 DCU Registers ........................................ 83
6.7.1 QCU Mask (D_QCUMASK) ..... 83
6.7.2 DCU-Specific IFS Settings
(D_LCL_IFS) ................................ 84
6.7.3 Retry Limits (D_RETRY_LIMIT) 84
6.7.4 ChannelTime Settings
(D_CHNTIME) ............................ 85
6.7.5 Misc. DCU-Specific Settings
(D_MISC) ..................................... 85
6.7.6 DCU-Global IFS Settings: SIFS
Duration (D_GBL_IFS_SIFS) ..... 87
6.7.7 DCU-Global IFS Settings: Slot
Duration (D_GBL_IFS_SLOT) .. 88
6.7.8 DCU-Global IFS Settings: EIFS
Duration (D_GBL_IFS_EIFS) .... 88
6.7.9 DCU-Global IFS Settings: Misc.
Parameters (D_GBL_IFS_MISC) 88
6.7.10 DCU Tx Pause Control/Status
(D_TXPSE) ................................... 89
6.7.11 DCU Transmission Slot Mask
(D_TXSLOTMASK) .................... 89
6.7.12 DCU Tx Filter Bits (D_TXBLK) . 91
EEPROM Interface Registers 93
6.8 Host Interface Registers ........................ 93
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 5
November 2011 • 5
Free Datasheet http://www.Datasheet4U.com
5 Page 
Table 1-1. Signal-to-Pin Relationships and Descriptions
Symbol
USB Pins
TXRTUNE
DM
DP
Radio
BIASREF
RF2INN
RF2INP
RF2OUTN
RF2OUTP
Analog Interface
PABIAS2N
PABIAS2P
PDET
XPABIAS
External Switch Control
SWCOM0
SWCOM1
SWCOM2
SWCOM3
General
RST_L
XTALI
XTALO
GPIO
GPIO0/TMS
GPIO1/TDI
GPIO2/TCK
GPIO4/TDO
GPIO5/SPISDO
GPIO6/SPIS_L
Pin Type Description
39 IA/OA Transmitter Resistor Tune Pin. Connects to an external
resistor of 51 Ω that adjusts the USB 2.0 PHY high-speed
source impedance.
40 IA/OA USB D- Signal. Carries USB data to and from the USB 2.0 PHY
38 IA/OA USB D+ Signal. Carries USB data to and from the USB 2.0
PHY
62 IA BIASREF voltage is 310 mV; must connect a 6.19 KΩ ± 1%
resistor to ground
2 IA Differential RF inputs. Use one side for single-ended input.
3 IA
6 IA/OA Differential RF power amplifier output. Differential RF input
7
IA/OA
for antenna 1. The RF amplifier output only appears on
antenna 1. There is a diversity switch inside the AR9271 that
selects antenna 1 or antenna 0 for baseband signal processing.
There is also a Tx/Rx switch for antenna 1.
9 IA Bias voltage for internal PA
4 IA
68 IA Input for optional external power detector
67 OA Bias for optional external power amplifier
13 O Common switch control
14 O
15 O
16 O
10 IH/OD Reset for the AR9271. This pin has an active open drain pull
down that forces it low if either the core or the IO supply is
below safe operating limits.
55 I 40 MHz crystal.
54 O
28 I/O General purpose and multiplexed for JTAG test mode
29 I/O General purpose and multiplexed for JTAG data input
30 I/O General purpose and multiplexed for JTAG test clock
31 I/O General purpose and multiplexed for JTAG data output
18 I/O General purpose and multiplexed serial output data from an
SPI device
19 I/O General purpose and multiplexed serial interface enable
signal of SPI
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 11
November 2011 • 11
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AR9271.PDF ] | |
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