PDF BU90R104 Data sheet ( Hoja de datos )

Número de pieza	BU90R104
Descripción	35bit LVDS Receiver 5:35 DeSerializer
Fabricantes	ROHM Semiconductor
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No Preview Available ! LVDS Interface ICs 35bit LVDS Receiver 5:35 DeSerializer BU90R104 No.13057ECT09 ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operates from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ●Features 1) Five channels of LVDS data stream are converted to 35bits data of parallel LVCMOS level outputs. 2) 30bits of RGB output data, 5bits of timing and control output data(HSYNC, VSYNC, DE, CTL1 and CTL2) are transmitted available. 3) Support clock frequency from 8MHz up to 112MHz. 4) Support consumer video format including 480i, 480P, 720P and 1080i as well. 5) Support many kinds of PC video formats such as VGA, SVGA, XGA and SXGA. 6) Provide 784Mbps per 1ch or 3.92Gbps per device throughput rate using 112MHz clock rate. 7) User programmable LVCMOS data output triggering timing by using either rising or falling edge of clock. 8) 30bit LVDS transmitter is recommended to use BU8254KVT. ●Applications Flat Panel Display ●Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Storage temperature range Symbol VDD VIN VOUT Tstg Ratings Min. Max. -0.3 4.0 -0.3 VDD+0.3 -0.3 VDD+0.3 -55 125 Unit V V V ℃ ●Package power Package PD(mW) DERATING(mW/℃) 1 TQFP64V 700 10002 7.0 10.02 1 At temperature Ta > 25℃ *2 Package power when mounting on the PCB board. The size of PCB board :70×70×1.6(mm3) The material of PCB board :The FR4 glass epoxy board.(3% or less copper foil area) ●Recommended operating conditions Parameter Ratings Symbol Min. Typ. Max. Supply voltage VDD 2.3 3.3 3.6 Unit Condition V VDD, LVDD, PVDD Supply Noise Voltage VNOZ - - 0.1 V -40 - 85 ℃ Clock frequency from 8MHz up to 90MHz Operating temperature range Topr 0 - 70 ℃ Clock frequency from 90MHz up to 112MHz www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/17 2013.06 - Rev.C Free Datasheet http://www.0PDF.com 1 page BU90R104 Technical Note ●Pin Description Pin Name RA+, RA- Pin No. 50,49 I/O LVDS Input Description RB+, RB- RC+, RC- RD+, RD- 52,51 55,54 60,59 LVDS Input LVDS data input LVDS Input + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair. LVDS Input RE+, RE- 62,61 LVDS Input RCLK+, RCLK- 57,56 LVDS Input LVDS clock input RA6～RA0 RB6～RB0 RC6～RC0 RD6～RD0 RE6～RE0 40,41,42,43, 45,46,47 32,33,34,35, 36,38,39 22,24,25,26, 27,28,29 14,15,17,18, 19,20,21 6,7,8,10, 11,12,13 Output Output Output LVCMOS data outputs. Output Output RESERVE PD 2 3 OE 4 R/F VDD 5 9,23,37,48 Input Input Input Input Power Reserved input must be “Low” for normal operation. Power down input for the internal system. H : Normal operation. L : Power down (All output are “Low”). Power down input for the data output driver. H : Output enable (Normal operation). L : Output disable (All outputs are “Hi-Z”). Select input pin for data output clock triggering edge. H : Output data is latched on rising edge. L : Output data is latched on falling edge. 3.3V output driver and digital core power supply pin. CLKOUT 31 Output LVCMOS level clock output. GND 1,16,30,44 Ground GND pin for both data output driver cells and the digital cores. LVDD 53 Power Power supply pin for LVDS inputs. LGND 58 Ground Ground pin for LVDS inputs. PVDD 64 Power Power supply pin for PLL core. PGND 63 Ground Ground pin for PLL core. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 5/17 2013.06 - Rev.C Free Datasheet http://www.0PDF.com 5 Page BU90R104 ●LVDS Data, Clock Input Timing Previous cycle RCLK + (Differential) Vdiff=0V Technical Note Current cycle tRCIP Vdiff=0V Next cycle RA+/- RA3 RA2 RA1 RA0 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6 RB+/- RB3 RB2 RB1 RB0 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB6 RC+/- RC3 RC2 RC1 RC0 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RC6 RD+/- RE+/- RD3 RD2 RD1 RD0 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD6 RE3 RE2 RE1 RE0 RE6 RE5 RE4 RE3 RE2 RE1 RE0 RE6 Fig.8 LVDS data and clock input timing www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/17 2013.06 - Rev.C Free Datasheet http://www.0PDF.com 11 Page

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Número de pieza	Descripción	Fabricantes
BU90R104	35bit LVDS Receiver 5:35 DeSerializer	ROHM Semiconductor

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