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PDF HI-5701 Data sheet ( Hoja de datos )
| Número de pieza | HI-5701 | |
| Descripción | 6-Bit/ 30MSPS/ Flash A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HI-5701
June 1999 File Number 2937.8
6-Bit, 30MSPS, Flash A/D Converter
The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers ±0.7 LSB
differential nonlinearity while consuming only 250mW (Typ)
at 30MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.
The HI-5701 is available in Commercial and Industrial
temperature ranges and is supplied in 18 lead Plastic DIP
and SOIC packages
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
NO.
HI3-5701K-5
0 to 70 18 Ld PDIP
E18.3
HI9P5701K-5
0 to 70 18 Ld SOIC
M18.3
HI3-5701B-9
-40 to 85 18 Ld PDIP
E18.3
HI9P5701B-9
-40 to 85 18 Ld SOIC
M18.3
HI5701-EV
25 Evaluation Board
Features
• 30MSPS with No Missing Codes
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . .300mW
• CMOS/TTL Compatible
• Overflow Bit
• /883 Version Available
Applications
• Video Digitizing
• Radar Systems
• Communication Systems
• High Speed Data Acquisition Systems
Pinout
HI-5701
(PDIP, SOIC)
TOP VIEW
D5 (MSB) 1
OVF 2
VSS 3
NC 4
CE2 5
CE1 6
CLK 7
PHASE 8
VREF+ 9
18 D4
17 D3
16 1/2R
15 D2
14 D1
13 D0 (LSB)
12 VDD
11 VIN
10 VREF-
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
HI-5701
Timing Waveforms
COMPARATOR DATA
ENCODED DATA IS
IS LATCHED
LATCHED INTO THE
OUTPUT REGISTERS
CLOCK
INPUT
PHASE - HIGH
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
CLOCK
INPUT
PHASE - LOW
ANALOG
INPUT
SAMPLE
N-2
AUTO
BALANCE
tAB
SAMPLE
N-1
tS
AUTO
BALANCE
SAMPLE
N
AUTO
BALANCE
SAMPLE
N+1
AUTO
BALANCE
SAMPLE
N+2
tAP
DATA
OUTPUT
DATA N - 4
tAJ
DATA N - 3
DATA N - 2
tH
tOD
DATA N - 1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2
tDIS tEN
D0 - D5
DATA
HIGH
IMPEDANCE
tDIS
tEN
DATA
HIGH
IMPEDANCE
DATA
OVF
DATA
HIGH
IMPEDANCE
DATA
FIGURE 2. OUTPUT ENABLE TIMING
5
5 Page 
HI-5701
TABLE 4. OUTPUT CODE TABLE (Continued)
CODE
DESCRIPTION
1/2 FS
1/4 FS
INPUT VOLTAGE†
VREF+ = 4V
VREF- = 0V
(V)
1.9688
•
•
•
0.9688
•
•
•
DECIMAL
COUNT
32
16
OVF
0
0
MSB
D5
1
0
BINARY OUTPUT CODE
D4 D3 D2
000
•
•
•
100
•
•
•
1 LSB
0.0313
1 00000
Zero 0 0 0 0 0 0 0
† The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
D1
0
0
0
0
LSB
D0
0
0
1
0
Glossary of Terms
Aperture Delay - is The time delay between the external
sample command (the rising edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter, tAJ - This is the RMS variation in the
aperture delay due to variation of internal φ1 and φ2 clock
path delays and variation between the individual comparator
switching times.
Differential Linearity Error, DNL - The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of each
midpoint is 1 LSB. The range of values possible is from
-1 LSB (which implies a missing code) to greater than
+1 LSB.
Full Power Input Bandwidth - Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude
of an input sine wave. The input sine wave has a peak-to-
peak amplitude equal to the reference voltage. The
bandwidth given is measured at the specified sampling
frequency.
Full Scale Error, FSE - is The difference between the actual
input voltage of the 63 to 64 code transition and the ideal
value of VREF+ - 1.5 LSB. This error is expressed in LSBs.
Integral Linearity Error, INL - The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are
calculated using a best fit line through the converter’s
transfer function.
LSB - Least Significant Bit = (VREF + - VREF -)/64. All
HI-5701 specifications are given for a 62.5mV LSB size
VREF+ = 4V, VREF- = 0V.
Offset Error, VOS - Offset error is the difference between
the actual input voltage of the 0 to 1 code transition and the
ideal value of VREF- + 0.5 LSB. VOS error is expressed in
LSBs.
Power Supply Rejection Ratio, PSRR - Is expressed in
LSBs and is the maximum shift in code transition points due
to a power supply voltage shift. This is measured at the 0 to
1 code transition point and the 62 to 63 code transition point
with a power supply voltage shift from the nominal value of
5.0V.
Signal to Noise Ratio, SNR - SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.
Signal to Noise and Distortion Ratio, SINAD - Is the ratio
in dB of the RMS signal to the RMS sum of the noise and
harmonic distortion at specified input and sampling
frequencies.
Total Harmonic Distortion, THD - Is the ratio in dBc of the
RMS sum of the first five harmonic components to the RMS
signal for a specified input and sampling frequency
11
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