STK544UC62K-E Datasheet PDF - ON Semiconductor
| Part Number | STK544UC62K-E | |
| Description | Intelligent Power Module | |
| Manufacturers | ON Semiconductor | |
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STK544UC62K-E
Intelligent Power Module (IPM)
600 V, 10 A
Overview
This Inverter IPM includes the output stage of a 3-phase inverter,
pre-drive circuits, bootstrap circuits, and protection circuits in one
package.
www.onsemi.com
Function
SIP (single in-line package) of the transfer full mold structure.
The emitter line of the each lower phase outputs to an external terminal
with the option of control using 3-phase current detection with external
resistors.
Direct input of CMOS level control signals without an insulating
circuit is possible.
Protective circuits including over current and pre-drive low voltage
protection are built in.
A single power supply drive is enabled through the use of bootstrap
circuits for upper IGBT gate drives.
Built-in dead-time for shoot-thru protection.
Internal substrate temperature is measured with an internal pulled up
thermistor.
Certification
UL1557 (File Number : E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
Collector-emitter voltage
VCC
VCE
V+ to VRU(VRV,VRW), surge < 500 V
V+ to U(V,W) or U(V,W) to VRU(VRV,VRW)
*1 450
600
V
V
Output current
Output peak current
Pre-driver voltage
Io
Iop
VD1,2,3,4
V+, VRU,VRV,VRW, U,V,W terminal current
V+, VRU,VRV,VRW, U,V,W terminal current at Tc = 100C
V+, VRU,VRV,VRW, U,V,W terminal current for a pulse width
of 1 ms
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
*2
±10
±6
±20
20
A
A
A
V
Input signal voltage
ITRIP terminal voltage
VIN
VITRIP
HIN1, 2, 3, LIN1, 2, 3 terminals
ITRIP terminal
0.3 to 7
VSS+5
V
V
Maximum power dissipation Pd
IGBT per 1 channel
22 W
Junction temperature
Tj
IGBT,FRD
150 C
Storage temperature
Tstg
40 to +125
C
Operating case temperature Tc
IPM case temperature
40 to +100
C
Tightening torque
Case mounting screws
*3 0.9
Nm
Withstand voltage
Vis 50 Hz sine wave AC 1 minute
*4
2000
VRMS
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : Surge voltage developed by the switching operation due to the wiring inductance between V+ and VRU(VRV,VRW) terminals.
*2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage.
*3 : Flatness of the heat-sink should be less than 50 m to +100 m.
*4 : Test conditions : AC 2500 V, 1 second.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
December 2016 - Rev. 3
1
Publication Order Number :
STK544UC62K-E/D
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STK544UC62K-E
Test Circuit
The tested phase U+ shows the upper side of the U phase and U- shows the lower side of the U phase.
■ ICE / IR(BD)
U+ V+ W+ U- V- W-
M
10 10 10
8
5
2
N 8 5 2 12 13 14
VD1=15V
VD2=15V
7
8
4
5
M
U(BD)
V(BD)
W(BD)
M 741
N 23 23 23
VD3=15V
VD4=15V
1
2
22
23
N
Fig. 1
ICE
A
VCE
■ VCE(SAT) (test by pulse)
U+ V+ W+ U- V- W-
M
10 10 10
8
5
2
N 8 5 2 12 13 14
m 15 16 17 18 19 20
■ VF (test by pulse)
U+ V+ W+ U- V- W-
M
10 10 10
8
5
2
N 8 5 2 12 13 14
VD1=15V
VD2=15V
VD3=15V
VD4=15V
7M
8
4
5
1
2
22
mN
23
21
Fig. 2
V
VCE(SAT)
Io
M
N
Fig. 3
V VF
Io
■ ID
M
N
VD1 VD2 VD3
741
852
VD4
22
23
ID
A
VD*
M
N
Fig. 4
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