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PDF ATTINY20 Data sheet ( Hoja de datos )
| Número de pieza | ATTINY20 | |
| Descripción | 8-bit AVR Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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ATtiny20
8-bit AVR Microcontroller
with 2K Bytes In-System Programmable Flash
DATASHEET
Features
High performance, low power 8-bit AVR® microcontroller
Advanced RISC architecture
112 powerful instructions – most single clock cycle execution
16 x 8 general purpose working registers
Fully static operation
Up to 12 MIPS throughput at 12MHz
Non-volatile program and data memories
2K bytes of in-system programmable flash program memory
128 bytes internal SRAM
Flash write/erase cycles: 10,000
Data retention: 20 years at 85oC / 100 years at 25oC
Peripheral features
One 8-bit timer/counter with two PWM channels
One 16-bit timer/counter with two PWM channels
10-bit analog to digital converter
8 single-ended channels
Programmable watchdog timer with separate on-chip oscillator
On-chip analog comparator
Master/slave SPI serial interface
Slave TWI serial interface
Special microcontroller features
In-system programmable
External and internal interrupt sources
Low power idle, ADC noise reduction, stand-by and power-down modes
Enhanced power-on reset circuit
Internal calibrated oscillator
I/O and packages
14-pin SOIC/TSSOP: 12 programmable I/O lines
12-ball WLCSP: 10 programmable I/O lines
15-ball UFBGA: 12 programmable I/O lines
20-pad VQFN: 12 programmable I/O lines
Operating voltage:
1.8 – 5.5V
Programming voltage:
5V
Speed grade
0 – 4MHz @ 1.8 – 5.5V
0 – 8MHz @ 2.7 – 5.5V
0 – 12MHz @ 4.5 – 5.5V
Industrial temperature range
Low power consumption
Active mode:
200 μA at 1MHz and 1.8V
Idle mode:
25μA at 1MHz and 1.8V
Power-down mode:
< 0.1μA at 1.8V
8235E–AVR–03/2013
Free Datasheet http://www.datasheet4u.com/
1 page  
2. Overview
ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
VCC
RESET
PROGRAMMING
LOGIC
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
ISP
INTERFACE
PROGRAM
COUNTER
STACK
POINTER
SRAM
INTERRUPT
UNIT
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
DATA REGISTER
PORT A
DIRECTION
REG. PORT A
DRIVERS
PORT A
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
RESET FLAG
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
SPI
TWI
8-BIT DATA BUS
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
ANALOG
COMPARATOR
ADC
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DRIVERS
PORT B
PA[7:0]
GND
PB[3:0]
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space
must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one
when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a
subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from
subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer
and the number of bits implemented is device dependent. In some AVR devices all data memory can be addressed using
SPL, only. In this case, the SPH register is not implemented.
The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of
SRAM. See Figure 5-1 on page 15.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
T1 T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two
register operands is executed, and the result is stored back to the destination register.
Figure 4-5. Single Cycle ALU Operation
T1
T2 T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATTINY20.PDF ] | |
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