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PDF MUN2211T1 Data sheet ( Hoja de datos )

Número de pieza MUN2211T1
Descripción Bias Resistor Transistors
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MUN2211T1 Series
Preferred Devices
Bias Resistor Transistors
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC−59 package which is designed for low power surface
mount applications.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Moisture Sensitivity Level: 1
ESD Rating − Human Body Model: Class 1
− Machine Model: Class B
The SC−59 Package can be Soldered Using Wave or Reflow
The Modified Gull−Winged Leads Absorb Thermal Stress During
Soldering Eliminating the Possibility of Damage to the Die
Pb−Free Packages are Available
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
VCBO
VCEO
IC
50 Vdc
50 Vdc
100 mAdc
Characteristic
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C
Derate above 25°C
PD 230 (Note 1) mW
338 (Note 2)
1.8 (Note 1) °C/W
2.7 (Note 2)
Thermal Resistance, Junction-to-Ambient RqJA
540 (Note 1) °C/W
370 (Note 2)
Thermal Resistance, Junction-to-Lead
RqJL
264 (Note 1) °C/W
287 (Note 2)
Junction and Storage Temperature
Range
TJ, Tstg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 x 1.0 inch Pad.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 12
1
http://onsemi.com
NPN SILICON
BIAS RESISTOR
TRANSISTORS
PIN 2
BASE
(INPUT)
R1
R2
PIN 3
COLLECTOR
(OUTPUT)
PIN 1
EMITTER
(GROUND)
3
2
1
SC−59
CASE 318D
STYLE 1
MARKING DIAGRAM
8x M G
G
1
8x = Device Code (Refer to page 2)
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the table on
page 2 of this data sheet.
DEVICE MARKING INFORMATION
See specific marking information in the Device Marking and
Resistor Values table on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MUN2211T1/D
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MUN2211T1 pdf
1
IC/IB = 10
0.1
0.01
MUN2211T1 Series
TYPICAL ELECTRICAL CHARACTERISTICS − MUN2211T1
TA = −25°C
25°C
75°C
1000
100
VCE = 10 V
TA = 75°C
25°C
−25°C
0.001 0
20 40 60
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) versus IC
80 10 1
10
IC, COLLECTOR CURRENT (mA)
Figure 3. DC Current Gain
100
4 100 25°C
f = 1 MHz
75°C
IE = 0 V 10 TA = −25°C
3 TA = 25°C
1
2
0.1
1
0.01
VO = 5 V
00
10 20
30 40
50 0.001 0 1 2 3 4 5 6 7 8 9 10
VR, REVERSE BIAS VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 4. Output Capacitance
Figure 5. Output Current versus Input Voltage
10
VO = 0.2 V
1
TA = −25°C
75°C
25°C
0.1 0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
Figure 6. Input Voltage versus Output Current
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MUN2211T1 arduino
MUN2211T1 Series
TYPICAL APPLICATIONS FOR NPN BRTs
+12 V
FROM mP OR
OTHER LOGIC
ISOLATED
LOAD
Figure 32. Level Shifter: Connects 12 or 24 Volt Circuits to Logic
+12 V
VCC
OUT
IN
LOAD
Figure 33. Open Collector Inverter:
Inverts the Input Signal
Figure 34. Inexpensive, Unregulated Current Source
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