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PDF ADM1184 Data sheet ( Hoja de datos )

Número de pieza ADM1184
Descripción 0.8% Accurate Quad Voltage Monitor
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo




1. ADM1184






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0.8% Accurate Quad Voltage Monitor
ADM1184
FEATURES
Powered from 2.7 V to 5.5 V on the VCC pin
Monitors 4 supplies via 0.8% accurate comparators
4 inputs can be programmed to monitor different voltage
levels with external resistor dividers
3 open-drain enable outputs (OUT1, OUT2, and OUT3)
Open-drain power-good output (PWRGD)
Internal 190 ms delay associated with assertion of PWRGD
10-lead MSOP
APPLICATIONS
Monitor and alarm functions
Telecommunications
Microprocessor systems
PC/servers
FUNCTIONAL BLOCK DIAGRAM
VCC
VIN1
VIN2
VIN3
VIN4
ADM1184
REF = 0.6V
REF = 0.6V
REF = 0.6V
REF = 0.6V
POWER AND
REFERENCE
REF = 0.6V
GENERATOR
INTERNAL
LOGIC
OUT1
OUT2
OUT3
PWRGD
GND
GENERAL DESCRIPTION
The ADM1184 is an integrated, 4-channel voltage-monitoring
device. A 2.7 V to 5.5 V power supply is required on the VCC pin
to power the device.
Four precision comparators monitor four voltage rails.
Each comparator has a 0.6 V reference with a worst-case
accuracy of 0.8%. Resistor networks that are external to the
VIN1, VIN2, VIN3, and VIN4 pins set the trip points for
the monitored supply rails.
The ADM1184 has four open-drain outputs. OUT1 to OUT3
can be used to enable power supplies, and PWRGD is a
common power-good output.
Figure 1.
OUT1 to OUT3 are dependent on their associated VINx input
(that is, VIN1, VIN2, or VIN3). If a supply monitored by VINx
drops below its programmed threshold, the associated OUTx pin
and PWRGD are disabled.
PWRGD is a common power-good output indicating the status
of all monitored supplies. There is an internal 190 ms (typical)
delay associated with the assertion of the PWRGD output. If
VIN1, VIN2, VIN3, or VIN4 drops below its programmed
threshold, PWRGD is deasserted immediately.
The ADM1184 is available in a 10-lead mini small outline
package (MSOP).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
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ADM1184 pdf
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM1184
GND 1
VIN1 2
VIN2 3
VIN3 4
VIN4 5
10 VCC
ADM1184
TOP VIEW
(Not to Scale)
9 OUT1
8 OUT2
7 OUT3
6 PWRGD
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Chip Ground Pin.
2 VIN1 Noninverting Input of Comparator 1. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider.
3 VIN2 Noninverting Input of Comparator 2. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider.
4 VIN3 Noninverting Input of Comparator 3. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider.
5 VIN4 Noninverting Input of Comparator 4. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider.
6
PWRGD
Active High, Open-Drain Output. When the voltage on each VINx input exceeds 0.6 V, PWRGD is asserted after a
190 ms delay. Once PWRGD has been asserted, if the voltage monitored by VIN1, VIN2, VIN3, or VIN4 falls below 0.6 V,
the PWRGD output is deasserted immediately.
7
OUT3
Active High, Open-Drain Output. When the voltage on VIN3 exceeds 0.6 V, OUT3 is asserted. OUT3 remains asserted
until the voltage monitored by VIN3 falls below 0.6 V, and then it is driven low.
8
OUT2
Active High, Open-Drain Output. When the voltage on VIN2 exceeds 0.6 V, OUT2 is asserted. OUT2 remains asserted
until the voltage monitored by VIN2 falls below 0.6 V, and then it is driven low.
9
OUT1
Active High, Open-Drain Output. When the voltage on VIN1 exceeds 0.6 V, OUT1 is asserted. OUT1 remains asserted
until the voltage monitored by VIN1 falls below 0.6 V, and then it is driven low.
10 VCC
Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.
Rev. 0 | Page 5 of 12
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ADM1184 arduino
ADM1184
VOLTAGE MONITORING AND SEQUENCING APPLICATION
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
VCC
ADM1184
VIN1
OUT1
VIN2
OUT2
VIN3
OUT3
VIN4
GND PWRGD
POWER
GOOD
IN
REGULATOR 1
EN OUT
GND
IN
REGULATOR 2
EN OUT
GND
2.5V OUT
1.8V OUT
IN
REGULATOR 3
EN OUT
GND
1.2V OUT
Figure 20. Voltage-Monitoring and Sequencing Application Diagram
Figure 20 depicts an application in which the ADM1184 monitors
four separate voltage rails, turns on three regulators in a sequence,
and generates a power-good signal to turn on a controller when
all power supplies are up and stable.
The main supply, in this case 3.3 V, powers up the device via the
VCC pin. The VIN1 pin monitors the main 3.3 V supply. In this
example application, OUT1 is connected to the enable pin of a
regulator. Before the voltage on VIN1 reaches 0.6 V, this output is
switched to ground, disabling Regulator 1.
The 2.5 V output of this regulator begins to rise and is detected
by input Pin VIN2. When VIN2 detects the 2.5 V rail rising
above its voltage threshold point, it asserts OUT2, which turns
on Regulator 2. The same scheme is implemented with the other
input and output pins. Every rail that is turned on via an output
pin, OUTx, is monitored via an input pin, VIN(x + 1).
When all four monitored supplies are above their programmed
threshold levels PWRGD asserts after a 190 ms (typical) delay.
When the main system voltage reaches 2.9 V, VIN1 detects 0.6 V.
This causes OUT1 to assert, which drives the enable pin of
Regulator 1 high, thus turning on its output.
Rev. 0 | Page 11 of 12
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