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PDF ML86410 Data sheet ( Hoja de datos )
| Número de pieza | ML86410 | |
| Descripción | Users Manual | |
| Fabricantes | OKI | |
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PEUL86410-02
Preliminary
ML86410 User’s Manual
Issue Date: December 20, 2006
Free Datasheet http://www.datasheet4u.com/
1 page  
ML86410 User’s Manual
Table of Contents
1. Overview ................................................................................................................................................ 1
1.1 Features.............................................................................................................................................. 1
1.2 Block Diagram ................................................................................................................................... 3
1.3 Pins ..................................................................................................................................................... 4
1.3.1 Pin Configuration ....................................................................................................................... 4
1.3.2 List of Pins .................................................................................................................................. 5
1.3.3 Pin Description ........................................................................................................................... 8
1.3.4 Pin Structure ............................................................................................................................ 12
1.3.5 Handling of Unused Pins ......................................................................................................... 14
2. Description of Software....................................................................................................................... 15
2.1 Register Description ........................................................................................................................ 15
2.1.1 List of Registers........................................................................................................................ 15
2.1.2 LSI Status Register (STATUS) ................................................................................................ 16
2.1.3 Interrupt Status Register (INTSTS) ....................................................................................... 18
2.1.4 Interrupt Mask Register (INTMSK) ....................................................................................... 19
2.1.5 External Interface Configuration Register (BUSIFCNFG) ................................................... 20
2.1.6 Output Stream Access Size Register (STRMACCSIZ) ........................................................... 21
2.1.7 DMA Signal Control Register (DMACNTL) ........................................................................... 22
2.1.8 Input Image Setup Register (INIMAGE)................................................................................ 23
2.1.9 Input Image Capture Mode Setting Register (IMGCPTMODE) ........................................... 25
2.1.10 Vertical Capture Start Pixel Setting Register (VSTART) .................................................. 27
2.1.11 Horizontal Capture Start Pixel Setting Register (HSTART) ............................................. 28
2.1.12 Input Image Data Range Conversion Setting Register (IMGRANGE) ............................. 29
2.1.13 Profile Setting Register (ENCPROFILE)............................................................................ 30
2.1.14 Coding Type Setting Register (CODINGTYPE).................................................................. 31
2.1.15 Rate Control Quantization Type Setting Register (RATECNTLTYPE) ............................ 32
2.1.16 Bit Rate Setting Registers 1,2 (BITRATE1, 2).................................................................... 34
2.1.17 Input Frame Skipping Setting Register (ENCFRAMERATE) .......................................... 36
2.1.18 Intra-Refresh Rate Setting Register (INTRAREFRESHRATE) ........................................ 37
2.1.19 Maximum Quantization Step Size Setting Register (MAXQUANT)................................. 38
2.1.20 Intra-Quantization Step Size Setting Register (INTRAQUANT) ..................................... 39
2.1.21 Inter-Quantization Step Size Setting Register (INTERQUANT)...................................... 40
2.1.22 Output Stream Register (STRMDATA)............................................................................... 41
2.1.23 Output Stream Size Registers 1, 2 (STRMSIZ1, STRMSIZ2) ........................................... 42
2.2 Initial Settings of the Registers...................................................................................................... 43
2.3 Standard Available Combinations (Use Cases) of Parameter Settings for MPEG Encoding . 44
3. Description of Operation..................................................................................................................... 47
3.1 States of Operation .......................................................................................................................... 47
3.1.1 Diagram of Transition of the States of Operation .................................................................. 48
3.2 Procedure for Activating MPEG-4 Encoding ................................................................................. 49
3.3 Procedure for Stream Data Transfer .............................................................................................. 52
3.3.1 Procedure for DMA Transfer.................................................................................................... 55
3.3.2 Procedure for Program Transfer.............................................................................................. 56
3.4 Procedure for Suspending/Restarting Encoding............................................................................ 58
3.5 Exception Processing ....................................................................................................................... 63
4. External Interface ............................................................................................................................... 64
4.1 Reset ................................................................................................................................................. 64
4.2 Video Interface ................................................................................................................................. 65
4.2.1 VSYNC/HSYNC Mode.............................................................................................................. 65
4.2.1.1 VSYNC/HSYNC Mode (VSYNC Level Mode )................................................................. 65
4.2.1.2 VSYNC/HSYNC Mode (VSYNC Edge Mode) .................................................................. 67
4.2.2 ITU-R BT.656 (SAV/EAV) Mode............................................................................................... 69
Contents − 1
Free Datasheet http://www.datasheet4u.com/
5 Page 
ML86410 User’s Manual
1.3.2 List of Pins
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
VDDPLL
GNDPLL
GNDIO
XI
XO
VDDIO
GNDCORE
VDDCORE
TMODE0
TMODE1
TMODE2
GNDIO
RSTN
VDDIO
XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
GNDCORE
XA9
VDDCORE
XD0
XD1
XD2
XD3
XD4
XD5
GNDCORE
VDDCORE
XD6
XD7
XD8
XD9
XD10
XD11
XD12
XD13
VDDCORE
XD14
XD15
GNDCORE
XCSN
VDDIO
XWEN
VDDCORE
I/O
VDD
GND
GND
—
—
VDD
GND
VDD
I
I
I
GND
I
VDD
I
I
I
I
I
I
I
I
I
GND
I
VDD
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
GND
I
VDD
I
VDD
Description
PLL power supply
PLL GND
I/O GND
Input clock (27 MHz)
Input clock (27 MHz)
I/O power supply
Core GND
Core power supply
Test mode 0
Test mode 1
Test mode 2
I/O GND
Reset
I/O power supply
External bus address input signal 0
External bus address input signal 1
External bus address input signal 2
External bus address input signal 3
External bus address input signal 4
External bus address input signal 5
External bus address input signal 6
External bus address input signal 7
External bus address input signal 8
Core GND
External bus address input signal 9
Core power supply
External bus input/output data 0
External bus input/output data 1
External bus input/output data 2
External bus input/output data 3
External bus input/output data 4
External bus input/output data 5
Core GND
Core power supply
External bus input/output data 6
External bus input/output data 7
External bus input/output data 8
External bus input/output data 9
External bus input/output data 10
External bus input/output data 11
External bus input/output data 12
External bus input/output data 13
Core power supply
External bus input/output data 14
External bus input/output data 15
Core GND
Chip enable signal
I/O power supply
Write enable signal
Core power supply
5
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11 Page | ||
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