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PDF DS1302 Data sheet ( Hoja de datos )
| Número de pieza | DS1302 | |
| Descripción | Trickle Charge Timekeeping Chip | |
| Fabricantes | TGS | |
| Logotipo |  |
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TIGER ELECTRONIC CO.,LTD
Trickle Charge Timekeeping Chip
DS1302
FEATURES
Real time clock counts seconds, minutes
hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 2100
31 x 8 RAM for scratchpad data storage
Serial I/O for minimum pin count
2.0–5.5V full operation
Uses less than 300 nA at 2.0V
Single–byte or multiple–byte (burst mode)
data transfer for read or write of clock or
RAM data
8–pin DIP or optional 8–pin SOICs for
surface mount
Simple 3–wire interface
TTL–compatible (VCC = 5V)
Optional industrial temperature range
–40°C to +85°C
DS1202 compatible
Recognized by Underwriters Laboratory
ORDERING INFORMATION
PART #
DS1302
DESCRIPTION
8–Pin DIP
DS1302N
8-Pin DIP (Industrial)
DS1302S
8–Pin SOIC (200 mil)
DS1302SN
8–Pin SOIC (Industrial)
DS1302Z
8–Pin SOIC (150 mil)
DS1302ZN
8–Pin SOIC (Industrial)
DS1302S-16
16-Pin SOIC (300 mil)
DS1302SN-16
16-Pin SOIC (Industrial)
PIN ASSIGNMENT
VCC2
X1
X2
GND
1
2
3
4
8 VCC1
7 SCLK
6 I/O
5 RST
DS1302
8-Pin DIP (300 mil)
VCC2
X1
1
2
8 VCC1
7 SCLK
X2 3
6 I/O
GND 4
5 RST
DS1302S 8-Pin SOIC (200 mil)
DS1302Z 8-Pin SOIC (150 mil)
VCC2
NC
X1
NC
X2
NC
NC
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
16-Pin SOIC
VCC1
NC
SCLK
NC
I/O
NC
NC
RST
PIN DESCRIPTION
X1, X2
– 32.768 kHz Crystal Pins
GND
– Ground
RST
I/O
SCLK
VCC1, VCC2
– Reset
– Data Input/Output
– Serial Clock
– Power Supply Pins
DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains a real time clock/calendar and 31 bytes of static
RAM. It communicates with a microprocessor via a simple serial interface. The real time clock/calendar
provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is
automatically adjusted for months with less than 31 days, including corrections for leap year. The clock
operates in either the 24–hour or 12–hour format with an AM/PM indicator
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Free Datasheet http://www.datasheet4u.com/
1 page  
DS1302
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5 volt is applied to VCC2 and a super cap is
connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1
between VCC2 and VCC1. The maximum current Imax would therefore be calculated as follows:
Imax = (5.0V – diode drop) / R1
~ (5.0V – 0.7V) / 2 kΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop between VCC2 and VCC1 will decrease and therefore
the charge current will decrease.
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst mode operation. In this mode the first eight
clock/calendar registers can be consecutively read or written (see Figure 4) starting with bit 0 of address
0.
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer
will occur to any of the eight clock/calendar registers (this includes the control register). The trickle
charger is not accessible in burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The
time information is read from these secondary registers, while the clock may continue to run. This
eliminates the need to re-read the registers in case of an update of the main registers during a read.
RAM
The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be
consecutively read or written (see Figure 4) starting with bit 0 of address 0.
REGISTER SUMMARY
A register data format summary is shown in Figure 4.
CRYSTAL SELECTION
A 32.768 kHz crystal can be directly connected to the DS1302 via X1 and X2. The crystal selected for
use should have a specified load capacitance (CL) of 6 pF. For more information on crystal selection and
crystal layout consideration, please consult Application Note 58, “Crystal Considerations with Real
Time Clocks."
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5 Page 
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
DS1302
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2.0V,
VOH=VCC for capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.0V,
VOL=GND for capacitive loads.
4. ICC1T and ICC2T are specified with I/O open, RST set to a logic “0”, and clock halt flag=0 (oscillator
enabled).
5. ICC1A and ICC2A are specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V;
SCLK=500 kHz, VCC=2.0V and clock halt flag=0 (oscillator enabled).
6. RST , SCLK, and I/O all have 40 kΩ pull–down resistors to ground.
7. Measured at VIH=2.0V or VIL=0.8V and 10 ns maximum rise and fall time.
8. Measured at VOH=2.4V or VOL=0.4V.
9. Load capacitance = 50 pF.
10. ICC1S and ICC2S are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic
one (oscillator disabled).
11. VCC=VCC2, when VCC2>VCC1 +0.2V; VCC=VCC1, when VCC1>VCC2.
12. VCC2=0V.
13. VCC1=0V.
14. Typical values are at 25°C.
11 of 14
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