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PDF AK5701 Data sheet ( Hoja de datos )
| Número de pieza | AK5701 | |
| Descripción | 16-Bit Stereo ADC | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK5701]
AK5701
16-Bit Stereo ADC with PLL & MIC-AMP
GENERAL DESCRIPTION
The AK5701 features a 16-bit stereo ADC. Input circuits include a Microphone-Amplifier and an ALC
(Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL
supports base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5701 is
available in a 24-pin QFN, utilizing less board space than competitive offerings.
FEATURES
1. Resolution: 16bits
2. Recording Function
- 2 Stereo Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: 1.8Vpp@VA=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
(+36dB 54dB, 0.375dB Step, Mute)
3. Sampling Rate:
- PLL Slave Mode (EXLRCK pin): 7.35kHz 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Slave Mode:
7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs)
4. PLL Input Clock:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s compliment
- DSP Mode, 16bit MSB justified, I2S
7. P I/F: 3-wire Serial
8. Power Supply:
- AVDD: 2.4 3.6V
- DVDD: 1.6 3.6V
9. Power Supply Current: 8mA
10. AK5701VN: Ta = 30 85C
AK5701KN: Ta = 40 85C
11. Package: 24-pin QFN (4mm x 4mm)
12. AEC-Q100 Qualified (AK5701KN)
MS0404-E-05
-1-
2015/11
1 page  
[AK5701]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter
Symbol
Min.
Power Supplies: Analog
AVDD
0.3
Digital
|AVSS – DVSS| (Note 3)
DVDD
GND
0.3
-
Input Current, Any Pin Except Supplies
IIN -
Analog Input Voltage (Note 4)
VINA
0.3
Digital Input Voltage (Note 5)
VIND
0.3
Ambient Temperature
AK5701VN Ta 30
(powered applied)
AK5701KN Ta 40
Storage Temperature
Tstg 65
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same analog ground plane.
Note 4. LIN1/LIN+, RIN1/LIN, LIN2/RIN, RIN2/RIN+ pins
Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
Max.
4.6
4.6
0.3
10
AVDD+0.3
DVDD+0.3
85
85
150
Unit
V
V
V
mA
V
V
C
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies Analog
AVDD
2.4 3.0 3.6 V
(Note 6) Digital
DVDD
1.6 3.0 AVDD V
Note 2. All voltages with respect to ground.
Note 6. The power-up sequence between AVDD and DVDD is not critical. When only AVDD is powered OFF, the power
supply current of DVDD at power-down mode may be increased. DVDD should not be powerd OFF while AVDD
is powered ON.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0404-E-05
-5-
2015/11
5 Page 
[AK5701]
Parameter
Control Interface Timing (CSP pin = “L”)
Symbol
Min.
CCLK Period
tCCK
142
CCLK Pulse Width Low
tCCKL
56
Pulse Width High
tCCKH
56
CDTI Setup Time
tCDS
28
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “” (Note 22)
CCLK “” to CSN Edge (Note 22)
Control Interface Timing (CSP pin = “H”)
tCDH
tCSW
tCSS
tCSH
28
150
50
50
CCLK Period
tCCK
142
CCLK Pulse Width Low
tCCKL
56
Pulse Width High
tCCKH
56
CDTI Setup Time
tCDS
28
CDTI Hold Time
CSN “L” Time
CSN Edge to CCLK “” (Note 22)
CCLK “” to CSN Edge (Note 22)
tCDH
tCSW
tCSS
tCSH
28
150
50
50
Power-down & Reset Timing
PDN Pulse Width (Note 23)
PMADL or PMADR “” to SDTO valid (Note 24)
HPF1-0 bits = “00”
HPF1-0 bits = “01”
HPF1-0 bits = “10”
tPD
tPDV
tPDV
tPDV
150
-
-
-
Note 22. CCLK rising edge must not occur at the same time as CSN edge.
Note 23. The AK5701 can be reset by the PDN pin = “L”.
Note 24. This is the count of LRCK “” from the PMADL or PMADR bit = “1”.
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3088
1552
784
Max.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
1/fs
1/fs
MS0404-E-05
- 11 -
2015/11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK5701.PDF ] | |
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