IT8511TE Datasheet PDF - ITE
Part Number | IT8511TE | |
Description | Embedded Controller | |
Manufacturers | ITE | |
Logo | ||
There is a preview and IT8511TE download ( pdf file ) link at the bottom of this page. Total 70 Pages |
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Embedded Controller
Preliminary Specification 0.4.1
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
Free Datasheet http://www.datasheet4u.com/
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IT8511E/TE/G
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 48
6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 48
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 48
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 48
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 48
6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 48
6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 49
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 49
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 49
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 49
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 49
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 50
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 50
6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 50
6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 50
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 50
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 50
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 51
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 51
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 51
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 51
6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 51
6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 51
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 52
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 52
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 52
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 52
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 52
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 52
6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 52
6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 53
6.2.8 Real Time Clock (RTC) Configuration Registers ................................................................. 53
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 53
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 53
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 54
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54
6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 54
6.2.8.8 RAM Lock Register (RLR) ....................................................................................... 54
6.2.8.9 Date of Month Alarm Register Offset (DOMAO) ..................................................... 55
6.2.8.10 Month Alarm Register Offset (MONAO) .................................................................. 55
6.2.8.11 P80L Begin Index (P80LB) ...................................................................................... 55
6.2.8.12 P80L End Index (P80LE)......................................................................................... 55
6.2.8.13 P80L Current Index (P80LC) ................................................................................... 55
6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 56
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 56
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 56
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 57
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 57
6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 57
6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 57
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 57
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 58
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ii IT8511E/TE/G V0.4.1
Free Datasheet http://www.datasheet4u.com/
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Information | Total 70 Pages | |
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