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What is AD7685?

This electronic component, produced by the manufacturer "Analog Devices", performs the same function as "250 kSPS PulSAR ADC".


AD7685 Datasheet PDF - Analog Devices

Part Number AD7685
Description 250 kSPS PulSAR ADC
Manufacturers Analog Devices 
Logo Analog Devices Logo 


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FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR)
SINAD: 93.5 dB @ 20 kHz
THD: −110 dB @ 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply operation 2.3 V to 5.5 V with
1.8 V to 5 V logic interface
Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Daisy-chain multiple ADCs, BUSY indicator
Power dissipation
1.4 μW @ 2.5 V/100 SPS
1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs
APPLICATIONS
Battery-powered equipment
Medical instruments
Mobile communications
Personal digital assistants (PDAs)
Data acquisition
Instrumentation
Process controls
2.0
POSITIVE INL = +0.33LSB
NEGATIVE INL = –0.50LSB
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
16384
32768
CODE
49152
Figure 1. Integral Nonlinearity vs. Code.
65536
16-Bit, 250 kSPS PulSAR
ADC in MSOP/QFN
AD7685
APPLICATION DIAGRAM
0.5V TO VDD 2.5V TO 5V
0 TO VREF
REF VDD VIO
IN+
SDI
AD7685 SCK
IN– SDO
GND
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
100
kSPS
250
kSPS
400 kSPS
to
500 kSPS
18-Bit True
AD7691 AD7690
Differential
AD7982
16-Bit True
AD7684 AD7687 AD7688
Differential
AD7693
16-Bit Pseudo AD7680 AD7685 AD7686
Differential AD7683 AD7694
14-Bit Pseudo AD7940 AD7942 AD7946
Differential
1000
kSPS
AD7982
AD7980
ADC
Driver
ADA4941
ADA4841
ADA4941
ADA4841
ADA4841
ADA4841
GENERAL DESCRIPTION
The AD7685 is a 16-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V to 5.5 V. It
contains a low power, high speed, 16-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile serial
interface port. The part also contains a low noise, wide bandwidth,
short aperture delay, track-and-hold circuit. On the CNV rising
edge, it samples an analog input IN+ between 0 V to REF with
respect to a ground sense IN−. The reference voltage, REF, is
applied externally and can be set up to the supply voltage.
Power dissipation scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single
3-wire bus or provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the
separate supply VIO.
The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/

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AD7685 equivalent
AD7685
TIMING SPECIFICATIONS
−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 4. VDD = 4.5 V to 5.5 V1
Parameter
Conversion Time: CNV Rising Edge To Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ Max Unit
0.5 2.2 μs
1.8 μs
4 μs
10 ns
15 ns
17 ns
18 ns
19 ns
20 ns
7 ns
7 ns
5 ns
14 ns
15 ns
16 ns
17 ns
15 ns
18 ns
22 ns
25 ns
15 ns
0 ns
5 ns
5 ns
3 ns
4 ns
15 ns
26 ns
1 See Figure 3 and Figure 4 for load conditions.
Rev. C | Page 5 of 28
Free Datasheet http://www.datasheet4u.com/


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AD7685 datasheet


1. 6-Bit, 250 kSPS, PulSAR ADC

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