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PDF USB3318 Data sheet ( Hoja de datos )
| Número de pieza | USB3318 | |
| Descripción | Hi-Speed USB Transceiver | |
| Fabricantes | SMSC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USB3318 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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USB3318
Hi-Speed USB Transceiver
with 1.8V-3.3V ULPI Interface -
13MHz Reference Clock
PRODUCT FEATURES
Data Brief
USB-IF “Hi-Speed” compliant to the Universal Serial
Bus Specification Rev 2.0
Interface compliant with the ULPI Specification
revision 1.1 as a Single Data Rate (SDR) PHY
1.8V to 3.3V IO Voltage (+/- 10%)
SMSC flexPWRTM Technology
— Low current design ideal for battery powered
applications
— “Sleep” mode tri-states all ULPI pins and places the
part in a low current state
Supports FS pre-amble for FS hubs with a LS device
attached (UTMI+ Level 3)
Supports HS SOF and LS keep-alive pulse
Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification
Supports the OTG Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
Allows host to turn VBUS off to conserve battery
power in OTG applications
Support OTG monitoring of VBUS levels with internal
comparators
“Wrapper-less” design for optimal timing performance
and design ease
— Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max) allows use of legacy UTMI Links with a ULPI
bridge
Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
13MHz Reference Clock operation
— 0 to 3.6V input drive tolerant
— Able to accept “noisy” clock sources
Internal low jitter PLL for 480MHz Hi-Speed USB
operation
Internal detection of the value of resistance to ground
on the ID pin
Integrated battery to 3.3V LDO regulator
— 2.2uF bypass capacitor
— 100mV dropout voltage
Integrated ESD protection circuits
— Up to +-15kV without any external devices
Carkit UART mode for non-USB serial data transfers
Industrial Operating Temperature -40°C to +85°C
Packaging Options
— 24 pin QFN lead-free RoHS compliant package
(4 x 4 x 0.90 mm height)
Applications
The USB3318 is targeted for any application where a Hi-
Speed USB connection is desired and when board
space, power, and interface pins must be minimized.
The USB3318 is well suited for:
Cell Phones
PDAs
MP3 Players
GPS Personal Navigation
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Entertainment Devices
Printers
Set Top Boxes
Video Record/Playback Systems
IP and Video Phones
Gaming Consoles
POS Terminals
SMSC USB3318
PRODUCT PREVIEW
Revision 1.3 (11-02-07)
Free Datasheet http://www.datasheet4u.com/
1 page  
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 13MHz Reference Clock
Table 1 USB3318 Pin Description (continued)
3
Power
N/A Regulator input. The regulator supply can
VBAT
be from 5.5V to 3.1V.
Power
N/A 3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
4
VDD3.3
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3318.
5 I/O, N/A D- pin of the USB cable.
DM Analog
6 I/O, N/A D+ pin of the USB cable.
DP Analog
Output,
CMOS
High
External 5 volt supply enable. This pin is
used to enable the external Vbus power
7 supply. The CPEN pin is low on POR.
CPEN
This pad uses VDD3.3 logic level.
8 I/O, N/A ULPI bi-directional data bus. DATA[7] is
DATA[7]
CMOS
the MSB.
9 I/O, N/A
DATA[6]
CMOS
ULPI bi-directional data bus.
10 I/O, N/A
DATA[5
CMOS
ULPI bi-directional data bus.
11 I/O, N/A
DATA[4]
CMOS
ULPI bi-directional data bus.
Output,
N/A 60MHz reference clock output. All ULPI
12
CMOS
signals are driven synchronous to the
CLKOUT
rising edge of this clock.
13 I/O, N/A
DATA[3]
CMOS
ULPI bi-directional data bus.
14 I/O, N/A
DATA[2]
CMOS
ULPI bi-directional data bus.
15 I/O, N/A
DATA[1]
CMOS
ULPI bi-directional data bus.
16 I/O, N/A ULPI bi-directional data bus. DATA[0] is
DATA[0]
CMOS
the LSB.
17
Power
N/A 1.8V to 3.3V ULPI interface supply
voltage. This voltage sets the value of
VDDIO
VOH for the ULPI interface.
Output,
High The PHY asserts NXT to throttle the data.
CMOS
When the Link is sending data to the
PHY, NXT indicates when the current
18
NXT
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
SMSC USB3318
5
PRODUCT PREVIEW
Revision 1.3 (11-02-07)
Free Datasheet http://www.datasheet4u.com/
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet USB3318.PDF ] | |
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