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PDF HV732 Data sheet ( Hoja de datos )

Número de pieza HV732
Descripción Integrated Ultrasound Pulser
Fabricantes Supertex 
Logotipo Supertex Logotipo



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No Preview Available ! HV732 Hoja de datos, Descripción, Manual

Supertex inc.
High Speed ±100V 2A
Integrated Ultrasound Pulser
HV732
Initial Release
Features
► HVCMOS technology for high performance
► 0 to ±100V output voltage
► ±2A source and sink current
► Built-in damping for RTZ waveform capability
► Gate-clamp for quick output amplitude ramping
► Up to 40MHz operation frequency
► ±3ns matched delay times
► Second harmonic is less than -40dB
► 1.8V to 3.3V CMOS logic interface
► 7x7 thermally-enhanced 44-lead QFN MCM
Application
► Medical ultrasound imaging
General Description
The Supertex HV732 is a single, complete, high-voltage,
high-speed, ultrasound transmitter pulser. It is designed for
medical ultrasound imaging applications.
The HV732 has built-in damping for faster RTZ waveform
capability and high voltage MOSFET gate-clamping function
for quick ramping of the output voltage amplitude.
The HV732 consists of a control logic circuit, level translators,
MOSFET gate drive buffers, clamp circuits, and high current,
high voltage MOSFETs as the ultrasound transmitter pulser
output stage.
In the output stage there are two pairs of MOSFETs. Each
pair consists of a P-channel and an N-channel MOSFET.
They are designed to have the same impedance, and can
provide peak currents of over ±2 amps. The built-in MOSFET
gate driver outputs swing 0 to 12V on P and N pins. The
DR DR
P-channel damp output swings 0 to –5V on the DMPO pin.
Typical Application Circuit
10nF
PIN
VSUB
CLAMP
VLL
VLN
EN
VDD
GND
NIN
AVDD
AGND
DAMP
PDR
PGATE
Level
Trans.
+12V
Buffer
Substrate, PAD1
+1.8 to 3.3V
-5V
on/off
+5 to 12V
0V
Level
Trans.
+12V
Buffer
Clamp
Circuit
Bias
Level
Trans.
NDR
NGATE
DMPO DMPI
VPP
0 to +100V
PAD3
PAD2
TXP
TXN
VNN
0 to -100V
HVOUT
OUTN
OUTP
RGNDP
RGNDN
10nF
10nF
NR040506
· · · ·Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com
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HV732 pdf
HV732
Logic Inputs
Symbol
tirf
VIH
VIL
IIH
IIL
Parameter
Inputs rise and fall time
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Min Typ Max Units Conditions
- - 10 ns Logic input edge speed requirement
0.8VLL - VLL V ---
0 - 0.2VLL V ---
- - 1.0 μA ---
-1.0 - - μA ---
AC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C)
Symbol Parameter
Min Typ Max Units Conditions
fout Output frequency range
tr Output rise time
- - 40 MHz See test curcuit and timing diagram
- 10 -
ns
tf Output fall time
tdr Delay time on rise time
- 10 -
- 12 -
ns See relevant test circuit and timing diagram.
ns Load = 1.0kΩ/220pF
tdf Delay time on fall time
- 12 -
ns
Δtdelay
HD2
Delay time matching
Second harmonic distortion
- - ±3.0 ns From device to device
- -40 -
dB 100Ω resistor load
tjitter
tEN
tDMPON(P)
tDMPOFF(P)
tDMPON(N)
tDMPOFF(N)
tCLPON(P)
tCLPOFF(P)
tCLPON(N)
tCLPOFF(N)
tPWRUP
Output jitter
Enable time
Damp switch on delay (P)
Damp switch off delay (P)
Damp switch on delay (N)
Damp switch off delay (N)
Clamp switch on delay (P)
Clamp switch off delay (P)
Clamp switch on delay (N)
Clamp switch off delay (N)
Device power-up delay
- 80 -
ps Standard deviation of td samples (1k)
- 30 50 μs See timing diagram
- 17 22 ns OUTP 50Ω to -15V, 10nF from DMPO to
- 20 26 ns DMPI. See timing diagram.
- 13 17 ns OUTN 50Ω to +15V.
- 13 17 ns See timing diagram.
-
430 1000
ns PGATE 75Ω to 0V, 10nF to PDR, VPP = +12V.
- 490 1000 ns See timing diagram.
- 330 550 ns NGATE 75Ω to 0V, 10nF to NDR, VNN = -12V.
- 316 500 ns See timing diagram.
- 150 200 μs All power supplies up and stable
Truth Table
Logic Control Inputs
EN PIN NIN CLAMP
1000
1100
1010
1XX1
1000
0XXX
DAMP
0
0
0
0
1
X
Gate Drive Output
PDR NDR DMPO
HLH
L LH
HHH
HLH
HLL
HLH
HV Output
TXP
OFF
TXN
OFF
ON OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
Damp Output
OUTP
OFF
OUTN
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON ON
OFF
OFF
NR040506
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