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PDF ISL94200 Data sheet ( Hoja de datos )
| Número de pieza | ISL94200 | |
| Descripción | Multi-Cell Li-ion Battery Pack OCP/Analog Front-End | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
July 3, 2008
ISL94200
FN6718.0
Multi-Cell Li-ion Battery Pack OCP/Analog
Front-End
The ISL94200 is an overcurrent protection device and
analog front end for a microcontroller in a multi-cell Li-ion
battery pack. The ISL94200 supports battery pack
configurations consisting of 4-cells to 7-cells in series and
1 or more cells in parallel. The ISL94200 provides integral
overcurrent protection circuitry, short circuit protection, an
internal 3.3V voltage regulator, cell voltage monitor level
shifters, and drive circuitry for external FET devices for
control of pack charge and discharge.
Selectable overcurrent and short circuit thresholds reside in
internal RAM registers. An external microcontroller sets the
thresholds by setting register values through an I2C serial
interface. Internal registers also contain the detection delays
for overcurrent and short circuit conditions.
Using an internal analog multiplexer the ISL94200 provides
monitoring of each cell voltage plus internal and external
temperature by a separate microcontroller with an A/D
converter. Software on this microcontroller implements all
battery pack control functionality, except for overcurrent and
short circuit shutdown.
Applications
• Power Tools
• Battery Backup Systems
• E-Bikes
• Portable Test Equipment
• Medical Systems
• Hybrid Vehicle
• Military Electronics
Ordering Information
PART NUMBER
PART
(Note)
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL94200IRZ 942 00IRTZ 24 Ld 4x4 QFN L24.4x4D
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Software Selectable Overcurrent Protection Levels and
Variable Protect Detection Times
- 4 Discharge Overcurrent Thresholds
- 4 Short Crcuit Thresholds
- 4 Charge Overcurrent Thresholds
- 8 Overcurrent Delay Times (Charge)
- 8 Overcurrent Delay Times (Discharge)
- 2 Short Circuit Delay Times (Discharge)
• Automatic FET Turn-Off On Reaching External (Battery) or
Internal (IC) Temperature Limit
• Fast Short Circuit Pack Shutdown
• Can Use Current Sense Resistor, FET rDS(ON), or Sense
FET for Overcurrent Detection
• Four Battery-Backed Software Controlled Flags
• Allows Three Different FET Controls:
- Back-to-Back N-Channel FETs for Charge and
Discharge Control
- Single N-Channel Discharge FET
- Single N-Channel FET for Discharge With Separate
Optional (Smaller) Back-to-Back N-Channel FETs for
Charge
http://www.DataSheet4U.net/
• Integrated Charge/Discharge FET Drive Circuitry With
130µA (Typ) Turn-On Current and 180mA (Typ) Discharge
FET Turn-Off Current
• 10% Accurate 3.3V Voltage Regulator (Minimum 25mA
Out With External NPN Transistor Having Current Gain
Of 70)
• Monitored Cell Voltage Output Stable in 100µs
• Simple I2C Host Interface
• Sleep Operation With Programmable Negative Edge or
Positive Edge Wake-Up
• <10µA Sleep Mode
• Pb-Free (RoHS compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
datasheet pdf - http://www.DataSheet4U.net/
1 page  
ISL94200
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS
Overcurrent Detection Threshold
(Discharge) Voltage Relative To
DSREF
(Default in Boldface)
Overcurrent Detection Threshold
(Charge) Voltage Relative to DSREF
(Default in Boldface)
Short Current Detection Threshold
Voltage Relative to DSREF
(Default in Boldface)
Load Monitor Input Threshold
(Falling Edge)
VOCD VOCD = 0.10V (OCDV1, OCDV0 = 0, 0)
VOCD = 0.12V (OCDV1, OCDV0 = 0,1)
VOCD = 0.14V (OCDV1, OCDV0 = 1,0)
VOCD = 0.16V (OCDV1, OCDV0 = 1,1)
VOCC VOCC = 0.10V (OCCV1, OCCV0 = 0, 0)
VOCC = 0.12V (OCCV1, OCCV0 = 0,1)
VOCC = 0.14V (OCCV1, OCCV0 = 1,0)
VOCC = 0.16V (OCCV1, OCCV0 = 1,1)
VSC VOC = 0.20V (SCDV1, SCDV0 = 0, 0)
VOC = 0.35V (SCDV1, SCDV0 = 0,1)
VOC = 0.65V (SCDV1, SCDV0 = 1, 0)
VOC = 1.20V (SCDV1, SCDV0 = 1,1)
VVMON LDMONEN bit = “1”
0.08
0.10
0.12
0.14
-0.12
-0.14
-0.16
-0.18
0.15
0.30
0.60
1.10
1.1
0.10
0.12
0.14
0.16
-0.10
-0.12
-0.14
-0.16
0.20
0.35
0.65
1.20
1.45
0.12
0.14
0.16
0.18
-0.07
-0.09
-0.11
-0.13
0.25
0.40
0.70
1.30
1.8
V
V
V
V
V
V
V
V
V
V
V
V
V
Load Monitor Input Threshold
(Hysteresis)
VVMONH LDMONEN bit = “1”
0.25 mV
Load Monitor Current
Short Circuit Time-out
IVMON
tSCD
Short circuit detection delay (SCLONGhttp://www.DataSheet4U.net/
bit = ‘0’)
20
90
40 60 µA
190 290 µs
Short circuit detection delay (SCLONG
bit = ‘1’)
5
10 15 ms
Over Discharge Current Time-out
(Default In Boldface)
tOCD tOCD = 160ms (OCDT1, OCDT0 = 0, 0
and DTDIV = 0)
80
160 240 ms
tOCD = 320ms (OCDT1, OCDT0 = 0, 1 and
160
320
480 ms
DTDIV = 0)
tOCD = 640ms (OCDT1, OCDT0 = 1, 0 and
320
640
960 ms
DTDIV = 0)
tOCD = 1280ms (OCDT1, OCDT0 = 1, 1
and DTDIV = 0)
640
1280
1920
ms
tOCD = 2.5ms (OCDT1, OCDT0 = 0, 0 and
1.25
2.50
3.75 ms
DTDIV = 1)
tOCD = 5ms (OCDT1, OCDT0 = 0, 1 and
2.5
5
7.5 ms
DTDIV = 1)
tOCD = 10ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 1)
5
10 15 ms
tOCD = 20ms (OCDT1, OCDT0 = 1, 1 and
10
20
30 ms
DTDIV = 1)
5 FN6718.0
July 3, 2008
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
ISL94200
Charge Overcurrent Monitor (Assumes DENOCC bit is ‘0’)
VCSENSE
VOCC
COC BIT
TEMP3V
OUTPUT
12V
CFET
OUTPUT
‘0’
tOCC
3.3V
‘1’
REGISTER 1 READ
µC TURNS ON CFE
Serial Interface Timing Diagrams
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
tSU:DAT
tHD:STA
SDA
(OUTPUT TIMING)
tHD:DAT
http://www.DataSheet4U.net/
tAA
tDH
tSU:STO
tBUF
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LOW
TO HIGH
MAY CHANGE
FROM HIGH
TO LOW
WILL CHANGE
FROM LOW
TO HIGH
WILL CHANGE
FROM HIGH
TO LOW
WAVEFORM
INPUTS
DON’T CARE:
CHANGES
ALLOWED
N/A
OUTPUTS
CHANGING:
STATE NOT
KNOWN
CENTER LINE
IS HIGH
IMPEDANCE
11
FN6718.0
July 3, 2008
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ISL94200.PDF ] | |
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