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PDF AD9558 Data sheet ( Hoja de datos )
| Número de pieza | AD9558 | |
| Descripción | Quad Input Multiservice Line Card Adaptive Clock Translator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad Input Multiservice Line Card Adaptive
Clock Translator with Frame Sync
AD9558
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually
no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
4 reference inputs (single-ended or differential)
Input reference frequencies: 2 kHz to 1250 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
6 pairs of clock output pins with each pair configurable as
a single differential LVDS/HSTL output or as 2 single-ended
CMOS outputs
Output frequencies: 352 Hz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional
feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths
from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking)
Low noise system clock multiplier
Frame sync support
Adaptive clocking
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation
configuration
Software controlled power-down
64-lead, 9 mm × 9 mm, LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and SDH to OTN mapping/demapping
Cleanup of reference clock jitter
SONET/SDH/OTN clocks up to 100 Gbps, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient control
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9558 is a low loop bandwidth clock multiplier that provides
jitter cleanup and synchronization for many systems, including
synchronous optical networks (OTN/SONET/SDH). The AD9558
generates an output clock synchronized to up to four external input
references. The digital phase-locked loop (PLL) allows reduction
of input time jitter or phase noise associated with the external
references. The digitally controlled loop and holdover circuitry
of the AD9558 continuously generates a low jitter output clock
even when all reference inputs have failed.
The AD9558 operates over an industrial temperature range of
−40°C to +85°C. If a smaller package is required, refer to the
AD9557 for the two-input/two-output version of the same device.
STABLE
SOURCE
FUNCTIONAL BLOCK DIAGRAM
CLOCK
MULTIPLIER
AD9558
REFERENCE INPUT
AND
MONITOR MUX
DIGITAL
PLL
ANALOG
PLL
÷3 TO ÷11
HF DIVIDER 0
÷3 TO ÷11
HF DIVIDER 1
FRAME SYNC
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CHANNEL 2
DIVIDER
CHANNEL 3
DIVIDER
SERIAL INTERFACE
(SPI OR I2C)
EEPROM
STATUS AND
CONTROL PINS
Figure 1.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9558
Changes to Address 0x0006, Address 0x0007, and
Address 0x000A, Table 35 ............................................................. 62
Changes to Address 0x0304, Table 35.......................................... 63
Changes to Address 0x0405, Table 35.......................................... 64
Changes to Address 0x071A and Address 0x071D, Table 35 ... 65
Changes to Address 0x0780, Address 0x0785 to
Address 0x078A, Address 0x079A, Address 0x079D, Table 35... 67
Changes to Address 0x07C0, Address 0x07DA, and
Address 0x07DD, Table 35 ............................................................ 68
Change to Address 0x0A01, Bit 7, Table 35 ................................ 69
Added Address 0x0E3D to Address 0x0E45, Table 35 .............. 71
Change to Table 38; Added Table 40, Renumbered Sequentially;
Changes to Table 41........................................................................ 72
Change to Bit 0, Address 0x0101, Table 43 ................................. 73
Changes to Address 0x0304, Table 55.......................................... 76
Deleted Address 0x0305, Table 55................................................ 76
Changes to Table Title, Table 63; Changes to Address 0x0400
and Address 0x0403, Table 64 ....................................................... 79
Changes to Address 0x0405, Table 64.......................................... 80
Changes to Descriptions, Address 0x0500, Table 67 ................. 81
Data Sheet
Changes to Bit 0, Address 0x0501, Table 68................................ 82
Changes to Bits[6:4], Address 0x0505 and Changes to
Address 0x0506, Table 70 .............................................................. 83
Changes to Bits[6:4] and Bit 0, Address 0x050F, Table 73 ........ 84
Change to Address 0x0704, Table 78; Changes to Bits[3:0] in
Address 0x0707 and Address 070A, Table 79; and Changes to
Address 0x070E, Table 82 ............................................................... 87
Changes to Address 0x0710, Table 83; and Changes to Bits[3:0],
Address 0x0714, Table 84 ................................................................ 88
Changes to Bits[1:0], Address 0x0A01, Table 90 .......................... 89
Changes to Descriptions, Address 0x0A0B, Table 99................ 91
Changes to Bit 4, Address 0x0C06, Table 100............................. 93
Changes to Bit 6 and Bit 1, Address 0x0D01, Table 102............ 94
Changes to Table Summary, Table 114 ........................................ 98
Added Table 128 ........................................................................... 101
Changes to Table 129 ................................................................... 102
Changes to Table 130 ................................................................... 103
10/2011—Revision 0: Initial Version
Rev. C | Page 4 of 105
5 Page 
AD9558
Data Sheet
DISTRIBUTION CLOCK OUTPUTS
Table 10.
Parameter
HSTL MODE
Output Frequency
Min
0.000352
Typ
Max
1250
Unit
MHz
Rise/Fall Time (20% to 80%)1
Duty Cycle
Up to fOUT = 700 MHz
Up to fOUT = 750 MHz
Up to fOUT = 1250 MHz
Differential Output Voltage Swing
Common-Mode Output Voltage
LVDS MODE
Output Frequency
45
42
700
700
0.000352
140
48
48
43
950
870
250
52
53
1200
960
1250
ps
%
%
%
mV
mV
MHz
Rise/Fall Time (20% to 80%)1
Duty Cycle
Up to fOUT = 750 MHz
Up to fOUT = 800 MHz
Up to fOUT = 1250 MHz
Differential Output Voltage Swing
Balanced, VOD
44
43
247
185 280
48 53
47 53
43
454
ps
%
%
%
mV
Unbalanced, ΔVOD
50 mV
Offset Voltage
Common-Mode, VOS
Common-Mode Difference, ΔVOS
Short-Circuit Output Current
CMOS MODE
Output Frequency
1.125
1.26 1.375
50
13 24
V
mV
mA
1.8 V Supply
3.3 V Supply (OUT0 and OUT5)
Strong Drive Strength Setting
Weak Drive Strength Setting
Rise/Fall Time (20% to 80%)1
1.8 V Supply
3.3 V Supply
Strong Drive Strength Setting
Weak Drive Strength Setting
Duty Cycle
1.8 V Mode
3.3 V Strong Mode
3.3 V Weak Mode
Output Voltage High (VOH)
AVDD3 = 3.3 V, IOH = 10 mA
AVDD3 = 3.3 V, IOH = 1 mA
AVDD3 = 1.8 V, IOH = 1 mA
Output Voltage Low (VOL)
AVDD3 = 3.3 V, IOL = 10 mA
AVDD3 = 3.3 V, IOL = 1 mA
AVDD3 = 1.8 V, IOL = 1 mA
0.000352
150 MHz
0.000352
0.000352
250 MHz
25 MHz
1.5 3
ns
0.4 0.6
8
ns
ns
50 %
47 %
51 %
AVDD3 − 0.3
AVDD3 − 0.1
AVDD − 0.2
V
V
V
0.3 V
0.1 V
0.1 V
Rev. C | Page 10 of 105
Test Conditions/Comments
OUT5 only; OUT0 to OUT4 minimum output
frequency is 360 kHz
100 Ω termination across output pins
Magnitude of voltage across pins; output driver static
Output driver static
OUT5 only; OUT0 to OUT4 minimum output
frequency is 360 kHz
100 Ω termination across the output pair
Voltage swing between output pins; output driver
static
Absolute difference between voltage swing of
normal pin and inverted pin; output driver static
Output driver static
Voltage difference between pins; output driver static
Output driver static
OUT5 only; OUT0 to OUT4 minimum output
frequency is 360 kHz
10 pF load
10 pF load
10 pF load
10 pF load
10 pF load
10 pF load
10 pF load
10 pF load
10 pF load
Output driver static; strong drive strength
Output driver static; strong drive strength
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9558.PDF ] | |
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