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PDF 39SF010A Data sheet ( Hoja de datos )
| Número de pieza | 39SF010A | |
| Descripción | SST39SF010A | |
| Fabricantes | SST | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 39SF010A (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
FEATURES:
SST39SF010A / 020A / 0405.0V 4Mb (x8) MPF memories
Preliminary Specification
• Organized as 128K x8 / 256K x8 / 512K x8
• Single 5.0V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 10 mA (typical)
– Standby Current: 30 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 45 and 70 ns
• Latched Address and Data
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39SF010A
4 seconds (typical) for SST39SF020A
8 seconds (typical) for SST39SF040
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF010A/020A/040 are CMOS Multi-Purpose
Flash (MPF) manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST39SF010A/020A/040 devices write
(Program or Erase) with a 5.0V power supply. The
SST39SF010A/020A/040 devices conform to JEDEC stan-
dard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF010A/020A/040 devices provide a maximum
Byte-Program time of 20 µsec. These devices use Toggle
Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, they have
on-chip hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF010A/020A/040 devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during erase and program than alter-
native flash technologies. The total energy consumed is a
www.DataSheet.net/
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF010A/020A/040 are offered in 32-pin PLCC and
32-pin TSOP packages. A 600 mil, 32-pin PDIP is also
available. See Figures 1, 2, and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
©2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
SST39SF040 SST39SF020A SST39SF010A
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)
SST39SF010A SST39SF020A SST39SF040
32
OE#
OE#
31 A10 A10
30 CE# CE#
29
DQ7
DQ7
28
DQ6
DQ6
27
DQ5
DQ5
26
DQ4
DQ4
25
DQ3
DQ3
24
VSS
VSS
23
DQ2
DQ2
22
DQ1
DQ1
21
DQ0
DQ0
20 A0 A0
19 A1 A1
18 A2 A2
17 A3 A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
389 ILL F01.1
SST39SF040 SST39SF020A SST39SF010A
SST39SF010A SST39SF020A SST39SF040
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 32-pin
7 PDIP
8 Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
www.DataSheet.net/
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
398 ILL F02a.2
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
©2001 Silicon Storage Technology, Inc.
5
S71147-02-000 5/01 398
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
ADDRESS AMS-0
CE#
TAS
OE#
WE#
DQ7-0
5555
TAH
TCP
2AAA
TCPH
5555
TCH
TCS
AA 55
A0
ADDR
INTERNAL PROGRAM OPERATION STARTS
TBP
TDH
TDS
DATA
SW0
SW1
SW2
BYTE
(ADDR/DATA)
Note: AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
www.DataSheet.net/
398 ILL F05.1
ADDRESS AMS-0
CE#
OE#
WE#
TOEH
TCE
TOE
DQ7
D D#
D#
Note: AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
11
TOES
D
398 ILL F06.1
S71147-02-000 5/01 398
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 39SF010A.PDF ] | |
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