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PDF SI2107 Data sheet ( Hoja de datos )
| Número de pieza | SI2107 | |
| Descripción | (SI2107 - SI2110) SATELLITE RECEIVER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SI2107 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Si2107/08/09/10
SATELLITE RECEIVER FOR DVB-S/DSS WITH
QUICKLOCK AND QUICKSCAN
Features
Single-chip tuner, demodulator,
and LNB controller
DVB-S- and DSS-compliant
QPSK/BPSK demodulation
Integrated step-up dc-dc
converter for LNB power supply
(Si2108/10 only)
Input signal level:
–82 to –10 dBm
Symbol rate range:
1 to 45 MBaud
Applications
Set-top boxes
Digital video recorders
Digital televisions
Automatic acquisition and fade
recovery
Automatic gain control
On-chip blind scan accelerator
with QuickScan (Si2109/10 only)
DiSEqC™ 2.2 support
Power, C/N, and BER estimators
I2C bus interface
3.3/1.8 V supply, 3.3 V I/O
Pb-free/RoHS-compliant
package
Satellite PC-TV
SMATV trans-modulators
(Satellite Master Antenna TV)
Description
www.DataSheet.net/
The Si2107/08/09/10 are a family of pin-compatible, complete front-end solutions
for DSS and DVB-S digital satellite reception. The IC family incorporates a tuner,
demodulator, and LNB controller into a single device resulting in significantly
reduced board space and external component count. The device supports symbol
rates of 1 to 45 MBaud over a 950 to 2150 MHz range. A full suite of features
including automatic acquisition, fade recovery, blind scanning, performance
monitoring, and DiSEqC Level 2.2 compliant signaling are supported. The Si2108/
10 further add short circuit protection, overcurrent protection, and a step-up dc-dc
controller to implement a low-cost LNB supply solution. Si2109/10 versions
include a hardware channel scan accelerator for fast “blindscan”. The Si2107/08/
09/10 family features new channel detection and acquisition technology:
QuickLock for Si2107/08/09/10 and QuickScan for Si2109/10. QuickLock
achieves fast channel acquisition and QuickScan, fast channel detection. An I2C
bus interface is used to configure and monitor all internal parameters.
Functional Block Diagram
Pin Assignments
Si2107/08/09/10
44 43 42 41 40 39 38 37 36
VDD_LNA 1
REXT 2
ADDR 3
VDD_MIX 4
VDD_BB 5
VDD_ADC 6
VSEN/TDET 7
LNB1/TGEN 8
ISEN 9
LNB2/DRC 10
RESET 11
PWM/DCS 12
VDD_DIG18 13
GND
Top
View
GND
35 XTAL1
34 XTAL2
33 VDD_XTAL
32 XTOUT
31 VDD_PLL33
30 INT/RLK/GPO
29 TS_ERR
28 TS_VAL
27 TS_SYNC
26 SDA
25 SCL
24 TS_DATA[7]
23 TS_DATA[6]
14 15 16 17 18 19 20 21 22
AGC
Acquisition Control
RFIP
Tuner
Demodulator
Viterbi
Decoder
RS
Decoder
VSEN/TDET
LNB2/DRC
ISEN/NC
LNB1/TGEN
PWM/DCS
LNB Control
RF Sythesizer
I2C Interface
XOUT
SCL SDA
TS_CLK
TS_DATA[7:0]
TS_VAL
TS_SYNC
TS_ERR
INT/RLK/GPO
Preliminary Rev. 0.81 6/06
Copyright © 2006 by Silicon Laboratories
Si2107/08/09/10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
Si2107/08/09/10
Table 3. DC Characteristics
(V3.3 = 3.3 V ±10%, V1.8 = 1.8 V ±10%, TA = 0–70 ºC)
Parameter
Supply Current, 3.3 V
Supply Current, 1.8 V
Symbol
I3.3
I1.8
Test Condition
45 Mbaud, CR 7/81
20 Mbaud, CR 2/31
45 Mbaud, CR 7/81
20 Mbaud, CR 2/31
Input high voltage
Input low voltage
Input leakage2
VIH SCL(25), SDA(26)
VIL SCL(25), SDA(26)
II SCL(25), SDA(26),
RESET(11),
XTAL1(35), VSEN/
TDET(7)
Output high voltage
Output low voltage
Output leakage
VOH
VOL
IOL
Notes:
1. LNB dc-dc converter disabled; LNB_EN (CEh[2]) = 0.
2. ISEN(9) is not tested for leakage current.
Min
—
—
—
—
2.3
0
—
2.4
—
—
Typ
313
298
292
217
—
—
—
—
—
—
Max
—
—
—
—
5.5
0.8
±10
—
0.4
±10
Unit
mA
mA
mA
mA
V
V
µA
V
V
µA
Table 4. RF Electrical Characteristics
Parameter
Input power, single channel
Aggregate input power
Input impedance, balanced
Return Loss
Symbol
Pi,ch
Pi,agg
Zin
Test Condition
www.DataSheet.net/
ZSOURCE = 75 Ω
Min Typ
— –821
——
— 75
— –10
Max
–10
–7
—
—
Unit
dBm
dBm
Ω
dB
Dynamic voltage gain range
Maximum voltage gain
Noise figure
IP3
∆GV
GV(max)
NF
IP33
Max gain2
Min gain2
— 75
—
— 55
—
— +9.5 +12.5
+5 +15
—
dB
dB
dB
dBm
LO leakage
LO SSB phase noise
LLO
950 to 2150 MHz
—
—
–70
dBm
100 kHz offset
— –97 –94 dBc/Hz
NLO
1 MHz offset
— –97 –94 dBc/Hz
LO DSB phase noise (integrated) NLO 10 kHz to 1/2 Baud —
Rate
2.1
2.8
°rms
RF synthesizer spurious
At 20 MHz offset — –40 — dBc/Hz
LO oscillator settling time
ts,LO
— 100
—
µs
Notes:
1. For a single channel with SR = 27.5 Mbaud, CR = 7/8, and no added noise. Input power range over which bit error rate
is less than 2e-4 after Viterbi decoder.
2. Max gain = 0hFFFF in AGC settings registers (25h–26h).
Min gain = 0h0000 in AGC settings registers (25h–26h).
3. IM3 can be calculated as follows: IM3 = 2 x (IP3 – Pin).
Preliminary Rev. 0.81
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
Si2107/08/09/10
8.5
8
7.5
7 975MHz
1550MHz
2150MHz
6.5 1318MHz
6
5.5
5
-100
-80 -60 -40 -20
Input Power (dBm)
0
Figure 4. Eb/No (QEF Operation) vs. Input Power for Si2107/08/09/10 (Typical)
SR = 27.5 MBaud, CR = 7/8
www.DataSheet.net/
1
0.1 27.5Mbaud 1/2
0.01
27.5Mbaud 2/3
0.001
0.0001
0.00001
0.000001
27.5Mbaud 3/4
27.5Mbaud 5/6
27.5Mbaud 7/8
0.0000001
0.00000001
2
4 6 8 10
Eb/No (dB)
All tests performed with 1550 MHz, –40 dBm input
Figure 5. BER After Viterbi vs. Eb/No for Si2107/08/09/10
Preliminary Rev. 0.81
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI2107.PDF ] | |
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