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RTL8306 Datasheet PDF - Realtek

Part Number RTL8306
Description (RTL8306 / RTL8308) 8/6-Port 10/100 Mbps Ethernet Switch Controller
Manufacturers Realtek 
Logo Realtek Logo 

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8308/8306 Preliminary Product Specification
Subject to change
Realtek 8/6-Port 10/100 Mbps
Ethernet Switch Controller
with Embedded memory
The RTL8308/8306 chip is a 128-pin low cost and ultra low power consumption 8/6-port
10/100M Ethernet switch controller integrated both with a 2M bits embedded DRAM as packet
buffer and a 16K entries of address table. The RTL8308 supports reduced MII (RMII) interface.
Only single 50MHz oscillator is needed in a switch system to save your Bill Of Material. In
addition, the RTL8308/8306 provides a LED display specially to indicate a network loop
existence.
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1. Features
n Support eight/six 10/100Mbps Ethernet ports
with RMII interface
n Provided non-blocking and non-head-of-line-
blocking forwarding
n 50MHz 2M bits DRAM is built in as packet
storage buffer. Page based buffer management
to efficiently utilize the internal packet buffer
n Ultra low power consumption with less than
180mA at 3.3V operating voltage
n Embedded 16K entries of look-up table and
128 entries of CAM
n Support address hashing or direct mapping for
look-up table. 128-entry CAM is used to
eliminate the hash collision problem
n Support full and half duplex operations
n Link, speed and duplex status are auto-
detected via MDIO
n Flow control fully supported:
l Half-duplex: back pressure
l Full-duplex: IEEE 802.3X
n Auto-negotiated Full-duplex flow control by
writing the ability via MDIO to external PHY
n Support store-and-forward and cut-through
n Provide a LED display especially to indicate a
network loop existence
n Broadcast storm control
n Reversible PHYAD order for diverse PHY
n 24C02 interface
n 128-pin PQFP, 0.35 um, 3.3V CMOS
technology
1 99/10/26
Datasheet pdf - http://www.DataSheet4U.net/

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RTL8306 equivalent
4. Functional Description
8308/8306 Preliminary Product Specification
Subject to change
Reset
After power on reset, the RTL8308/8306 will determine some features from ENFCTRL, ENBRDCTRL
and ENLOOP pins, auto-load the content of 24C02 serial EEPROM, and write abilities to connected PHY
management registers via MDC/MDIO. It is most important that the RTL8308/8306 and connected PHYs
have to use the same reset signal source. Otherwise, it is not guaranteed to work properly.
RMII interface
The RTL8308/8306 provides 10/100 Mbps low pin count RMII interface for use between PHY and
RTL8308/8306. The RMII is capable of supporting 10Mbps and 100Mbps data rates. A single clock
reference, 50MHz, sourced from an external clock input is used for receive and transmit. It also provides
independent 2 bit wide (di-bit) transmit and receive data paths. As the REFCLK is 10 times the data rate
in 10Mbps mode each data di-bit must be output on TXD[1:0] and input on RXD[1:0] for ten consecutive
REFCLK cycles. The RTL8308/8306 can regenerate the COL signal of the MII internally by ANDing
TXEN and CRS as recovered from CRSDV. Note that TXEN cannot be ANDed directly with CRSDV
since CRSDV may toggle at the end of the frame to provide separation of RXDV and CRS.
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RMII Specification Signals are as below,
Signal Name
REFCLK
CRSDV
RXD[1:0]
TXEN
TXD[1:0]
Direction
(with respect
to the PHY)
Input
Output
Output
Input
Input
Direction
Use
(with respect
to the
RTL8308/8306)
Input
Synchronous clock reference for receive,
transmit and control interface.
Input
Carrier Sense/Receive Data Valid
Input
Receive Date
Output
Transmit Enable
Output
Transmit Data
Serial Management Interface MDC/MDIO
The RTL8308/8306 supports PHY management through the serial MDIO and MDC signal lines. After
power on reset, the RTL8308/8306 write abilities to the advertisement register 4 of connected PHY and
restart the auto-negotiation process through MDIO using PHY address increasingly from 01000b to
01111b. After restarting auto-negotiation, the RTL8308/8306 will continuously poll the link status and
link partner's ability which including speed, duplex and flow control of the PHY devices via MDIO. The
following is the management frame format
5 99/10/26
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