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19-5709; Rev 0; 12/10
EVAALVUAAILTAIOBNLEKIT
Rail-to-Rail, 200kHz Op Amp
with Shutdown in a Tiny, 6-Bump WLP
General Description
The MAX44265 op amp features a maximized ratio of
gain bandwidth (GBW) to supply current and is ideal for
battery-powered applications such as handsets,
tablets, notebooks, and portable medical equipment.
This CMOS op amp features an ultra-low input-bias cur-
rent of 1pA, rail-to- rail input and output, low supply cur-
rent of 4µA, and operates from a single 1.8V to 5.5V
supply. For additional power conservation, the IC also
features a low-power shutdown mode that reduces sup-
ply current to 1nA and puts the amplifier’s outputs in a
high-impedance state. This device is unity-gain stable
with a 200kHz GBW product.
It is available in a space-saving, 0.9mm x 1.3mm,
6-bump WLP package and is specified over the -40°C
to +85°C extended operating temperature range.
Applications
Cell Phones
Tablet/Notebook Computers
Mobile Accessories
Battery-Powered Devices
Features
♦ 200kHz GBW
♦ Ultra-Low 4µA Supply Current
♦ Single 1.8V to 5.5V Supply Voltage Range
♦ Ultra-Low 1pA Input Bias Current
♦ Rail-to-Rail Input and Output Voltage Ranges
♦ Low ±200µV Input Offset Voltage
♦ Low 0.001µA Shutdown Current
♦ High-Impedance Output During Shutdown
♦ Unity-Gain Stable
♦ Available in a Tiny, 0.9mm x 1.3mm, 6-Bump WLP
Package
Ordering Information
PART
TEMP RANGE
MAX44265EWT+ -40°C to +85°C
PIN-
PACKAGE
6 WLP
TOP
MARK
+BY
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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Rail-to-Rail, 200kHz Op Amp
with Shutdown in a Tiny, 6-Bump WLP
Typical Operating Characteristics
(VDD = 3V, VSS = VCM = 0V, RL to VDD/2, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
9
8
7
6
5 TA = +25°C TA = -40°C
4
3
TA = +85°C
2
1
1.8
2.6 3.4 4.2
VSUPPLY (V)
5.0 5.5
200
150
100
50
0
-50
-100
-150
-200
-250
-300
-350
-40
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
-15 10 35 60
TEMPERATURE (°C)
85
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
0
-20
-40
-60
-80
-100
-120
0.1
1 10 100 1k
FREQUENCY (Hz)
10k
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
12
10
8
6
4
2
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
7
6
5
4
3
2
1
0
-1
-2
-3
-40
INPUT BIAS CURRENT
vs. TEMPERATURE
IB-
IB+
-15 10 35 60
TEMPERATURE (°C)
85
COMMON-MODE REJECTION RATIO
vs. TEMPERATURE
140
120
100
80
60
40
20
0
-40 -15 10 35 60
TEMPERATURE (°C)
85
INPUT OFFSET VOLTAGE
vs. INPUT COMMON-MODE VOLTAGE
1000
750
500 TA = -40°C
250 TA = +25°C
0
-250
-500
-750
-1000
0
TA = +85°C
0.5 1.0 1.5 2.0 2.5 3.0
VCM (V)
INPUT BIAS CURRENT
vs. INPUT COMMON-MODE VOLTAGE
5
4
3
2
1
0
-1
-2
-3
-4
-5
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCM (V)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
10 100 1k 10k
FREQUENCY (Hz)
100k
_______________________________________________________________________________________ 5
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Rail-to-Rail, 200kHz Op Amp
with Shutdown in a Tiny, 6-Bump WLP
Power-Supply Considerations
The IC is optimized for single 1.8V to 5.5V supply oper-
ation. A high amplifier power-supply rejection ratio of
95dB (typ) allows the devices to be powered directly
from a battery, simplifying design and extending bat-
tery life.
Power-Up Settling Time
The IC typically requires 5µs after power-up. Supply
settling time depends on the supply voltage, the value
of the bypass capacitor, the output impedance of the
incoming supply, and any lead resistance or induc-
tance between components. Op-amp settling time
depends primarily on the output voltage and is slew-
rate limited. Figure 3 shows MAX44265 in a noninvert-
ing voltage follower configuration with the input held at
midsupply. The output settles in approximately 18µs for
VDD = 3V (see the Typical Operating Characteristics for
power-up settling time).
Shutdown Mode
The IC features an active-low shutdown input. The
device enters shutdown in 2µs (typ) and exit in 30µs
(typ). The amplifier’s outputs are in a high-impedance
state in shutdown mode. Drive SHDN low to enter shut-
down. Drive SHDN high to enable the amplifier.
5.5V
0V
100kΩ
100kΩ
IN- VDD
MAX44265
IN+
VSS
OUT
Figure 3. Power-Up Test Configuration
Power-Supply Bypassing and Layout
To minimize noise, bypass VDD with a 0.1µF capacitor
to ground, as close to the pin as possible.
Good layout techniques optimize performance
by decreasing the amount of stray capacitance and
inductance to the op amps’ inputs and outputs.
Minimize stray capacitance and inductance by placing
external components close to the IC.
PROCESS: BiCMOS
Chip Information
______________________________________________________________________________________ 11
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