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Número de pieza | HT16C23 | |
Descripción | LCD Driver Controller | |
Fabricantes | Holtek Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de HT16C23 (archivo pdf) en la parte inferior de esta página. Total 35 Páginas | ||
No Preview Available ! HT16C23/HT16C23Gwww.DataSheet.co.kr
RAM Mapping 56*4 / 52*8
LCD Driver Controller
Features
●● Operating voltage: 2.4 ~ 5.5V
●● Internal 32kHz RC oscillator
●● Bias: 1/3 or 1/4; Duty:1/4 or 1/8
●● Internal LCD bias generation with voltage-
follower buffers
●● I2C-bus interface
●● Two Selectable LCD frame frequencies: 80Hz or
160Hz
●● Up to 52 x 8 bits RAM for display data storage
●● Display patterns:
––56 x 4 patterns: 56 segments and 4 commons
––52 x 8 patterns: 52 segments and 8 commons
●● Versatile blinking modes
●● R/W address auto increment
●● Internal 16-step voltage adjustment to adjust LCD
operating voltage
●● Low power consumption
●● Provides VLCD pin to adjust LCD operating voltage
●● Manufactured in silicon gate CMOS process
●● Package Type: 48LQFP, 64LQFP, Chip and
Goldbump chip.
Applications
●● Electronic meter
●● Water meter
●● Gas meter
●● Heat energy meter
●● Household appliance
●● Games
●● Telephone
●● Consumer electronics
General Description
The HT16C23/HT16C23G device is a memory
mapping and multi-function LCD controller driver.
The Display segments of the device are 224 patterns
(56 segments and 4commons) or 416 patterns (52
segments and 8commons). The software configuration
feature of the HT16C23/HT16C23G device makes it
suitable for multiple LCD applications including LCD
modules and display subsystems. The HT16C23/
HT16C23G device communicates with most
microprocessors / microcontrollers via a two-line
bidirectional I2C-bus.
Block Diagram
VSS
SDA
SCL
Power_on reset
I2C
Controller
Internal RC
Oscillator
8 Display RAM
52*8bits
Timing
generator
VDD
VCCA2
VLCD
Internal
voltage
adjustment
-
OP4
+
R-
OP3
+
R-
OP2
+
R-
OP1
+
R
LCD bias generator
LCD
Voltage
Selector
Column
/Segment
driver
output
COM0
COM3
COM4/SEG0
COM7/SEG3
SEG4
Segment
driver
output
SEG55
Rev. 1.10
1 June 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/
1 page www.DataSheet.co.kr
HT16C23/HT16C23G
Pad Assignment for Goldbump Chip
1 94 93
54 53 52
2 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 51
3
4
5
6
7
(0, 0)
8
9
10
11
12
13
14
16 17 18 19 20 21 22
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
15
50
49
48
47
46
45
44
43
42
41
40
39
38
Note:
●● VLCD (pad 21) must be connected to VCCA2 (pad 22) in the PCB layout for the application at VDD ≤ VLCD or
VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
DE bit
VE bit
VLCD
(pad 21)
SEG55
(pad 14)
Note
0
0
Input
Null ●●VLCD support internal bias voltage.
0
1
Input
Null
●●Internal Voltage Adjustment is null
●●VLCD support internal bias voltage
1
0
Input
Output
●●VLCD support internal bias voltage
1
1
Input
Output
●●VLCD support internal bias voltage
●● VDD (pad 19) must be connected to VCCA2 (pad 22) in the PCB layout for the application at VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
DE bit
VE bit
VLCD
(pad 21)
SEG55
(pad 14)
Note
0
0
Input
Null ●●VLCD support internal bias voltage.
0
1
Output
Null
●●Detect the internal bias voltage
●●VDD support internal bias voltage
1
0
Floating
Output
●●VDD support internal bias voltage
1
1
Floating
Output
●●VDD support internal bias voltage
Rev. 1.10
5 June 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page www.DataSheet.co.kr
Timing Diagrams
I2C timing
HT16C23/HT16C23G
SDA
tf
tLOW
tr
tSU:DAT
SCL
SDA
OUT
tHD:STA
S
tHD:DAT
tAA
tHIGH
Power On Reset timing
tHD:STA
tSU:STA
Sr
tBUF
tSP
tSU:STO
PS
Rev. 1.10
11
June 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page |
Páginas | Total 35 Páginas | |
PDF Descargar | [ Datasheet HT16C23.PDF ] |
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