|
|
PDF FM28V100 Data sheet ( Hoja de datos )
| Número de pieza | FM28V100 | |
| Descripción | 1Mbit Bytewide F-RAM Memory | |
| Fabricantes | Ramtron | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de FM28V100 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
www.DataSheet.co.kr
Preliminary
FM28V100
1Mbit Bytewide F-RAM Memory
Features
1Mbit Ferroelectric Nonvolatile RAM
• Organized as 128Kx8
• High Endurance 100 Trillion (1014) Read/Writes
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process
Superior to Battery-backed SRAM Modules
• No battery concerns
• Monolithic reliability
• True surface mount solution, no rework steps
• Superior for moisture, shock, and vibration
SRAM Replacement
• JEDEC 128Kx8 SRAM pinout
• 60 ns Access Time, 90 ns Cycle Time
Low Power Operation
• 2.0V – 3.6V Power Supply
• Standby Current 90 µA (typ)
• Active Current 7 mA (typ)
Industry Standard Configurations
• Industrial Temperature -40° C to +85° C
• 32-pin “Green”/RoHS Package
General Description
The FM28V100 is a 128K x 8 nonvolatile memory
that reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and very high write endurance make
F-RAM superior to other types of memory.
In-system operation of the FM28V100 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by toggling a chip enable pin
or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric
memory process. These features make the FM28V100
ideal for nonvolatile memory applications requiring
frequent or rapid writes in the form of an SRAM.
Device specifications are guaranteed over the
industrial temperature range -40°C to +85°C.
Pin Configuration
A11
A9
A8
A13
WE
CE2
A15
VDD
NC*
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP-I
32 OE
31 A10
30 CE1
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
* Reserved for A17 on 2Mb
Ordering Information
FM28V100-TG
32-pin “Green”/RoHS TSOP
FM28V100-TGTR 32-pin “Green”/RoHS TSOP,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
May 2010
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 13
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is prepared for a new
access. Precharge is user-initiated by driving at least
one of the chip enable signals to an inactive state. The
chip enable must remain inactive for at least the
minimum precharge time tPC.
Precharge is also activated by changing the upper
addess A(16:3). The current row is first closed prior
FM28V100 - 128Kx8 FRAM
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the tAA address
access time. Refer to the Read Cycle Timing 1
diagram on page 9. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 11. The rate at which
random addresses can be issued is tRC and tWC,
respectively.
Endurance
The FM28V100 is capable of being accessed at least
1014 times – reads or writes. An F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A16-A3
and column addresses by A2-A0. The array is
organized as 16K rows of 8-bytes each. The entire
row is internally accessed once whether a single byte
or all eight bytes are read or written. Each byte in the
row is counted only once in an endurance calculation.
The user may choose to write CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address, 7
page mode accesses, and a CE precharge. The
number of bus clocks needed to complete an 8-byte
transaction is 8+1 at lower bus speeds, but 9+2 at
33MHz due to initial read latency and an extra clock
to satisfy the device’s precharge timing constraint tPC.
The entire loop causes each byte to experience only
one endurance cycle. F-RAM read and write
endurance is virtually unlimited even at 33MHz
system bus clock rate.
Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq Bus Cycle 256-byte Endurance Endurance Years to
(MHz) Time (ns) Transaction Cycles/sec. Cycles/year Reach 1014
Time (µs)
Cycles
33
30
10.56
94,690
2.98 x 1012
33.5
25
40
12.8
78,125
2.46 x 1012
40.6
10
100
28.8
34,720
1.09 x 1012
91.7
5
200
57.6
17,360
5.47 x 1011
182.8
Rev. 1.2
May 2010
Page 5 of 13
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
FM28V100 - 128Kx8 FRAM
Write Cycle Timing 3 (/CE1 low, CE2 high) Note: /OE is low only to show effect of /WE on DQ pins
Page Mode Write Cycle Timing
Although sequential column addressing is shown, it is not required.
Power Cycle Timing
VDD min
VDD
t VR
t PU
t VF
Access Allowed
VDD min
t PD
Rev. 1.2
May 2010
Page 11 of 13
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FM28V100.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| FM28V100 | 1Mbit Bytewide F-RAM Memory | Ramtron |
| FM28V100 | 1-Mbit (128 K x 8) F-RAM Memory |  Cypress Semiconductor |
| FM28V102A | 1-Mbit (64 K x 16) F-RAM Memory | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |