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PDF AN601 Data sheet ( Hoja de datos )
| Número de pieza | AN601 | |
| Descripción | Unclamped Inductive Switching Rugged MOSFETs | |
| Fabricantes | Vishay Siliconix | |
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AN601
Vishay Siliconix
Unclamped Inductive Switching Rugged MOSFETs
For Rugged Environments
The evolution of the power MOSFET has resulted in a very
rugged transistor. The semiconductor industry defines this
ruggedness as the capability to withstand avalanche currents
when subjected to unclamped inductive switching. Historically,
MOSFET manufacturers chose to quantify ruggedness, not
based principally on individual performance, but rather on
comparative performance with other manufacturers. Siliconix
has optimized the cell structure of power MOSFETs, resulting
in a new class of extremely rugged devices. Today’s
avalanche-rated MOSPOWER FET exhibits a ruggedness
that far exceeds the performance of any power MOSFET of
earlier years.
Symbols and Definitions
Whenever possible, symbols and definitions established by
the JEDEC Committee, JC-25, are used in this article. To clear
up any discrepancies, however, the following list describes
symbols used frequently in this article.
IO the peak current reached during avalanche
tAV the time duration of the avalanche phenomenon
L the value of inductance
V(BR)eff the breakdown voltage in avalanche
This application note reviews the history of unclamped
inductive switching (UIS) and examines various theories
pertaining to failure. It further identifies what appears to be two
related mechanisms — thermal and bipolar — believed to be
responsible for failure during unclamped inductive switching
and concludes by recommending how a power MOSFET
should be qualified for ruggedness in the data sheet.
Two failure modes exist when MOSFETs are subjected to UIS.
In this article, these failure mechanisms are labelled as either
active or passive. The first, or active mode, results when the
avalanche current forces the parasitic bipolar transistor into
conduction. The second, or passive mode, results when the
instantaneous chip temperature reaches a critical value.[1] At
this elevated temperature, a “mesoplasma”* forms within the
parasitic npn bipolar transistor and causes catastrophic
thermal runaway. In either case, the MOSFET is destroyed.
The passive mechanism is, therefore, identified as that failure
mode not directly attributed to avalanche currents.
What is Unclamped Inductive Switching?
Whenever current through an inductance is quickly turned off,
the magnetic field induces a counter electromagnetic force
(EMF) that can build up surprisingly high potentials across the
switch. Mechanical switches often have spark-suppression
circuits to reduce these harmful effects that result when current
is suddenly interrupted. However, when transistors are used
as the switches, the full buildup of this induced potential may
far exceed the rated breakdown (V(BR)DSS) of the transistor,
thus resulting in catastrophic failure.
If we know the size of the inductor, the amount of current being
switched, and the speed of the switch, the expected potential
may be easily calculated as
V = L di/dt + VDD
(1)
where
L = the inductance (H)
di/dt = rate of change of current (A/s)
VDD = the supply voltage (V)
*A “mesoplasma,” according to Ghandhi, takes the form of a glowing red spot having an average temperature in excess of 650_C and a peak
core temperature in excess of 1000_C. This mesoplasma is a result of regenerative thermal runaway.
Document Number: 70572
15-Feb-94
www.vishay.com S FaxBack 408-970-5600
1
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AN601
Vishay Siliconix
Test Results
The Siliconix avalanche-rated SMP30N10 is one of a family of
dense-cell MOSPOWER FETs. Cell density for this family is
1.6M/in.2 (248K/cm2). The overall chip area is 0.17 cm2.
UIS avalanche breakdown was examined at a variety of
inductance values (0.01 to 10 mH) at starting temperatures
from ambient (25_C) to 150_C in 25_C increments. A sample
size of 20 pieces for each inductance and at each temperature
involved over 760 MOSFETs. All MOSFETs were from the
same wafer lot.
The test method used the alternate circuit which removed VDD
immediately prior to switching. The equipment used, a ITC UIS
Tester,* Model 5510E, allowed an increase of current, IO, in
0.1-A increments to 26 A and thereafter in 1.0-A increments.
A fixed gate-drive impedance of 25 W drove the device under
test. A temperature-controlled heater was used to sink the
power MOSFET (mounted in the TO-220 package) to provide
a precise starting temperature throughout the UIS tests.
80
70
L = 0.05 mH
60 L = 0.1 mH
50
L = 0.3 mH
40
L = 1.0 mH
30
L = 3.0 mH
20
10 L = 10 mH
0
0 25 50 75 100 125 150 175
Temperature (_C)
FIGURE 5. Avalanche Failure Current vs. Starting
Temperature for the SMP30N10
as dramatically nor with the tight convergence described by
Stoltenburg.[4] Since Figure 5 represents the culmination of
incremental increases in avalanche current, these data
conclusively show that if Siliconix avalanche-rated power
MOSFETs are operated within data sheet limits, they can enter
into avalanche without fear of failure. Furthermore, these data
tend to confirm that absolute maximum ratings are not so
absolute as once thought. At the 150_C starting temperature
and switching 32 A (at 1 mH), the calculated chip temperature,
see equation (4), is 322_C!
The typical 2.2 mV/_C decay of VBE and the increasing
resistance of the p-doped region with increasing temperature
suggests that the parasitic npn bipolar transistor becomes
more susceptible to turn-on with increasing temperature.
Although a rapid fall-off of avalanche current at higher
temperatures might be anticipated because of this increased
susceptibility, Figure 5 shows a reasonably slow decline. This
behavior is attributed to the slow lateral spreading of the
current along the p/n junction as the avalanche current
increases. The dense cell design diminishes lateral spreading
of avalanche current beyond the heavily doped p+ (Zener)
region and, thus, enables more avalanche current than
MOSFETs with less dense cell structures.
The measured data (see Figure 5) may be manipulated, with
the help of equation (2), to identify interesting details of UIS
phenomenon. Figure 6 plots avalanche failure current versus
inductance across a temperature range from ambient to
150_C.
100
25_C
150_C
10
Figure 5 shows avalanche current versus starting
temperature for six values of inductance, ranging from 0.05 to
10 mH. These data represent single-event UIS failures and
further identify that the device ratings, in particular the
“absolute maximum ratings” of IAR and TJ, are conservative.
For any given inductance, the avalanche failure current
decreased as the starting temperature increased, although not
1
0.01
0.1 1.0
Inductance (mH)
10
FIGURE 6. Avalanche Failure Current vs. Inductance
for the SMP30N10
*Integrated Technology Corporation, 1228 N. Stadem Drive, Tempe, Arizona 85281
Document Number: 70572
15-Feb-94
www.vishay.com S FaxBack 408-970-5600
5
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