PDF U6206B Data sheet ( Hoja de datos )

Número de pieza	U6206B
Descripción	1.3 GHz PLL
Fabricantes	TEMIC Semiconductors
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No Preview Available ! www.DataSheet.co.kr TELEFUNKEN Semiconductors 1.3 GHz PLL for TV- and VCR- Tuner U6206B Description The U6206B is a single chip PLL frequency synthesizer with unidirectional I2C bus control. This IC contains a high frequency prescaler which can be switched off. 5 open collector switching outputs are available. Features D 1.3 GHz divide-by-8 prescaler integrated (can be bypassed) D 15 bit counter accepts input frequencies up to 170 MHz D m P-controlled by I2C-Bus D 5 switching outputs (open collector ) D 4 addresses selectable at Pin 8 for multituner application D 62.5 kHz (–1.3 GHz)/ 7.8125 kHz (–170 MHz) tuning steps D Electrostatic protection according to MILSTD 883 D SO16 small package Package: SO16 Block Diagram ADDRESS SELECTION (AS) 8 SW1 SW4 SW0 SW2 SW7 11 10 9 7 6 SCL 5 SDA 4 I2 C–BUS CONTROL 5 BIT LATCH SWITCHING OUTPUTS 7 BIT LATCH 8 BIT LATCH 5 BIT LATCH T1 GATE 14 RFi 13 15 BIT LATCH 1 OR 8 PRESCALER 15 BIT COUNTER PSC T0 5I PHASE CHARGE COMPAR. PUMP 12 15 Vs GND OSC 23 CRYSTAL 512 Figure 1. OS 16 VD 1 PD 95 10723 Rev. A1: 25.10.1995 1 (8) Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr TELEFUNKEN Semiconductors U6206B Oscillator Frequency Calculation fosc = fref * SF * PSF fosc: Locked oscillator frequency fref : Reference frequency 4MHz /512 = 7.8125 kHz SF: Scaling factor of programmable 15-bit- divider PSF: Scaling factor of prescaler Pulse Diagram ADDRESS BYTE / A / 1.BYTE / A / 2.BYTE / A / 3.BYTE / A / 4.BYTE / A / SDA SCL START 1 2 3 4 5 6 7 8 9 1... 8 9 1... Figure 2. 8 9 1... 8 9 1... 8 9 STOP 95 10724 Data transfer examples START – ADR – PDB1 – PDB2 – CB1 – CB2 – STOP START – ADR – CB1 – CB2 – –PDB1 – PDB2 – STOP START – ADR – PDB1 – PDB2 – CB1 – STOP START – ADR – CB1 – CB2 – PDB1 – STOP START – ADR – PDB1 – PDB2 – STOP START – ADR – CB1 – CB2 – STOP START – ADR – CB1 – STOP Description START= Start condition ADR= Address byte PDB1= Progr.divider byte 1 PDB2= Progr. divider byte 2 CB1= Control byte 1 CB2= Control byte 2 STOP= Stop condition Bus Timing t W STA SDA SCL t S STA t LOW t HIGH tt RF t H STA START CLOCK t S DAT t H DAT DATACHANGE Figure 3. 95 10725 t S STO STOP tS STA tW STA tH STA tLOW tHIGH – Set – up time start – Waiting time start – Hold time start – ”L” – Pulse width clock – ”H” – Pulse width clock Rev. A1: 25.10.1995 tS DAT tH DAT tS STO tR tF – Set – up time data – Hold time data – Set – up time stop – Rise time – Fall time 5 (8) Datasheet pdf - http://www.DataSheet4U.net/ 5 Page

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