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PDF M28F102 Data sheet ( Hoja de datos )
| Número de pieza | M28F102 | |
| Descripción | 1 Mbit Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28F102
1 Mbit (64Kb x16, Bulk) Flash Memory
5V ± 10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 90ns
BYTE PROGRAMMING TIME: 10µs typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
– Stand-by Current: 5µA typical
10,000 ERASE/PROGRAM CYCLES
OTP COMPATIBLE PACKAGES and PINOUT
INTEGRATED ERASE/PROGRAM-STOP
TIMER
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 0050h
PLCC44 (K)
TSOP40 (N)
10 x 14mm
Figure 1. Logic Diagram
DESCRIPTION
The M28F102 Flash memory is a non-volatile
memory that may be erased electrically at the chip
level and programmed by word. It is organised as
64 Kwords of 16 bits. It uses a command register
architectureto select the operatingmodes and thus
provides a simple microprocessor interface. The
device is offered in PLCC44 and TSOP (10 x
14mm) packages.
Table 1. Signal Names
A0 - A15
Address Inputs
DQ0 - DQ15
Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
August 1998
VCC VPP
16
A0-A15
16
DQ0-DQ15
W M28F102
E
G
VSS
AI00627B
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M28F102
to start the erase operation. Erasure starts on the
rising edge of W during this second cycle.
Erase is followed by an Erase Verify which reads
an addressed byte.
Erase Verify Mode is set-up by writing ’xxA0h’ to
the command register and at the same time sup-
plying the address of the word to be verified. The
rising edge of W during the set-up of the first Erase
Verify Mode stops the Erase operation. The follow-
ing read cycle is made with an internally generated
margin voltage applied; reading 0FFFFh indicates
that all bits of the addressed byte are fully erased.
The whole contents of the memory are verified by
repeating the Erase Verify Operation, first writing
the set-up code ’xxA0h’ with the address of the
word to be verified and then reading the byte
contents in a second read cycle.
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not 0FFFFh, an-
other Erase operation is performedand verification
continuesfrom the address of the last verifiedword.
The command is terminated by writing another
valid command to the command register (for exam-
ple Program or Reset).
Program and Program Verify Modes. The Pro-
gram Mode is set-up by writing ’xx40h’ to the com-
mand register. This is followed by a second write
cycle which latches the address and data of the
word to be programmed. The rising edge of W
during this secind cycle starts the programming
operation. Programming is followed by a Program
Verify of the data written.
ProgramVerify Mode is set-up by writing ’xxC0h’ to
the command register. The rising edge of W during
the set-up of the Program Verify Mode stops the
Programming operation. The following read cycle,
of the address already latched during program-
ming, is made with an internally generated margin
voltage applied, reading valid data indicates that all
bits have been programmed.
Reset Mode. This command is used to safelyabort
Erase or Program Modes. The Reset Mode is
set-up and performed by writing 0FFFFh two times
to the command register. The command should be
Table 6. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
≤ 10ns
0.45V to 2.4V
Input and Output Timing Ref. Voltages 0.8V to 2V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 3. AC Testing Input Output Waveforms
2.4V
0.45V
2.0V
0.8V
AI00827
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI00828
Table 7. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested
VIN = 0V
VOUT = 0V
Min Max Unit
6 pF
12 pF
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M28F102
Table 10B. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10% or 5V ± 5%)
M28F102
Symbol Alt
Parameter
-150
Standard
Interface
-200
Standard
Int erface
Min Max Min Max
tVPHEL
VPP High to Chip Enable Low
tVPHWL
VPP High to Write Enable Low
tWHWH3
tWC Write Cycle Time (W controlled)
tEHEH3
tWC Write Cycle Time (E controlled)
tAVWL
tAS Address Valid to Write Enable Low
tAVEL
Address Valid to Chip Enable Low
tWLAX
tAH Write Enable Low to Address Transition
tELAX
Chip Enable Low to Address Transition
tELWL
tCS Chip Enable Low to Write Enable Low
tWLEL
Write Enable Low to Chip Enable Low
tGHWL
Output Enable High to Write Enable Low
tGHEL
Output Enable High to Chip Enable Low
tDVWH
tDS Input Valid to Write Enable High
tDVEH
Input Valid to Chip Enable High
tWLWH
tWP Write Enable Low to Write Enable High (Write Pulse)
tELEH
Chip Enable Low to Chip Enable High (Write Pulse)
tWHDX
tDH Write Enable High to Input Transition
tEHDX
Chip Enable High to Input Transition
tWHWH1
Duration of Program Operation (W controlled)
tEHEH1
Duration of Program Operation (E controlled)
tWHWH2
Duration of Erase Operation (W controlled)
tEHEH2
Duration of Erase Operation (E controlled)
tWHEH
tCH Write Enable High to Chip Enable High
tEHWH
Chip Enable High to Write Enable High
tWHWL
tWPH Write Enable High to Write Enable Low
tEHEL
Chip Enable High to Chip Enable Low
tWHGL
Write Enable High to Output Enable Low
tEHGL
Chip Enable High to Output Enable Low
tAVQV
tELQX (1)
tACC Addess Valid to data Output
tLZ Chip Enable Low to Output Transition
tELQV
tGLQX (1)
tCE Chip Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
tGLQV
tEHQZ (1)
tGHQZ (1)
tOE Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
tAXQX
tOH Address Transition to Output Transition
Note: 1. Sampled only, not 100% tested
11
11
150 200
150 200
00
00
60 75
80 80
20 20
00
00
00
50 50
50 50
60 60
70 80
10 10
10 10
9.5 9.5
9.5 9.5
9.5 9.5
9.5 9.5
00
00
20 20
20 20
66
66
150 200
00
150 200
00
70 70
55 60
35 45
00
Unit
µs
µs
ns
120
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
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| PDF Descargar | [ Datasheet M28F102.PDF ] | |
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