IT8512F Datasheet PDF - ITE
| Part Number | IT8512F | |
| Description | Embedded Controller | |
| Manufacturers | ITE | |
| Logo |  |
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There is a preview and IT8512F download ( pdf file ) link at the bottom of this page. Total 70 Pages | ||
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IT8512E/F
Embedded Controller
Preliminary Specification 0.4.1
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
Datasheet pdf - http://www.DataSheet4U.net/
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IT8512E/F
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 46
6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 46
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 46
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 47
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 47
6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 47
6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 47
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 47
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 47
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 48
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 48
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 48
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 48
6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 48
6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 48
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 49
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 49
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 49
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 49
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 49
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 49
6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 49
6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 50
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 50
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 50
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 50
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 50
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 51
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 51
6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 51
6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 51
6.2.8 BRAMLD Configuration Registers........................................................................................ 52
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 52
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 52
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 52
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 52
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 53
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 53
6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 53
6.2.8.8 P80L Begin Index (P80LB) ...................................................................................... 53
6.2.8.9 P80L End Index (P80LE)......................................................................................... 53
6.2.8.10 P80L Current Index (P80LC) ................................................................................... 53
6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 54
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 54
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 54
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 55
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 55
6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 55
6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 55
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 55
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 56
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 56
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ii IT8512E/F V0.4.1
Datasheet pdf - http://www.DataSheet4U.net/
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IT8512F electronic component. |
| Information | Total 70 Pages | |
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| Download | [ IT8512F.PDF Datasheet ] | |
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