PDF AKM4352 Data sheet ( Hoja de datos )

Número de pieza	AKM4352
Descripción	2V & LOW POWER MULTI-BIT DAC
Fabricantes	Asahi Kasei Microsystems
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No Preview Available ! www.DataSheet.co.kr ASAHI KASEI [AK4352] AK4352 2V & Low Power Multi-Bit ∆Σ DAC GENERAL DESCRIPTION The AK4352 is an 18bit low voltage & power stereo DAC for digital audio system. The AK4352 uses the new developed Multi-Bit ∆Σ architecture, this new architecture achieves DR=94dB at low voltage operation. The AK4352 includes post filter with single-ended output and does not need any external parts. The AK4352 is suitable for the portable audio system like MD, etc as low power and small package. FEATURES • Multi-Bit ∆Σ DAC • Sampling Rate Ranging: 8kHz ∼ 50kHz • On chip post filter • On chip Buffer with Single-ended Output • On chip Perfect filtering 8 times FIR interpolator Passband: 20kHz Passband Ripple: ± 0.06dB Stopband Attenuation: 43dB • Digital Audio I/F format: 2’s compliment, MSB first 18bit MSB justified, 16/18bit LSB justified, I2S • Digital de-emphasis for 44.1kHz sampling • Master clock: 256fs or 384fs • THD+N: -83dB@2V, -89dB@3V • D-Range: 94dB@2V, 96dB@3V • Output Voltage: 1.10Vpp@2V • Low Voltage Operation: 2V (1.8 ∼ 3.6V) • Low power Dissipation: 6mW@2V • Very Small Package: 16pin TSSOP DIF0 DIF1 LRCK BICK SDATA VDD VSS PD Serial Input Interface 8X Interpolator ∆Σ Modulator De-emphasis Control 8X Interpolator ∆Σ Modulator Clock Divider LPF LPF VCML AOUTL AOUTR VCMR DEM MCLK CKS VREF M0040-E-02 -1- 2000/11 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr ASAHI KASEI [AK4352] FILTER CHARACTERISTICS (Ta=25°C; VDD=1.8 ∼ 3.6V; fs=44.1kHz; DEM= “L”) Parameter Symbol min typ Digital filter Passband -0.1dB (Note 6) PB 0 -6.0dB - 22.05 Stopband (Note 6) SB 24.1 Passband Ripple PR Stopband Attenuation SA 43 Group Delay (Note 7) GD - 14.7 Digital Filter + Analog Filter Frequency Response 0 ∼ 20.0kHz - ± 0.2 max 20.0 - ± 0.06 - - Units kHz kHz kHz dB dB 1/fs dB Note 6. The passband and stopband frequencies scale with fs. For example, PB=0.4535fs(@-0.1dB), SB=0.546fs(@-43dB). Note 7. The calculating delay time which occurred by digital filtering. This time is from setting the 18bit data of both channels to input register to the output of analog signal. (Ta=25°C; VDD=1.8 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current DIGITAL CHARACTERISTICS Symbol VIH VIL Iin min 75%VDD - - typ - - - max - 25%VDD ± 10 Units V V µA M0040-E-02 -5- 2000/11 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr ASAHI KASEI [AK4352] 1. Grounding and Power Supply Decoupling Figure 6 shows the power supply connection example. VDD is supplied from analog supply in system. Decoupling capacitors for high frequency should be as near to the AK4352 device as possible, with the low value ceramic capacitor between VREF and VSS being the nearest. 2. Voltage Reference The differential Voltage between VREF and VSS sets the analog output range. VREF pin is normally connected to VDD. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor are attached between VREF and VSS pins. VCML and VCMR pins are a signal ground of this chip. An electrolytic capacitor less than 10µF parallel with a 0.1µF ceramic capacitor attached between VCML, VCMR pins and VSS eliminates the effects of high frequency noise. Especially, the ceramic capacitor should be connected to these pins as near as possible. No load current may be drawn from VCML and VCMR pins. All signals, especially clocks, should be kept away from the VREF, VCML and VCMR pins in order to avoid unwanted coupling into the AK4352. 3. Analog Outputs The analog outputs are single-ended and centered around the VCML, VCMR voltage. The output signal range is typically 1.10Vpp. If the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCML, VCMR voltage for 0000H(@16bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCML, VCMR voltage + a few mV. M0040-E-02 - 11 - 2000/11 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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