|
|
PDF CY14V101LA Data sheet ( Hoja de datos )
| Número de pieza | CY14V101LA | |
| Descripción | 1-Mbit (128 K x 8/64 K x 16) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY14V101LA (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
CY14V101LA
CY14V101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
■ 25 ns and 45 ns access times
■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16
(CY14V101NA)
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power down
■ RECALL to SRAM initiated by software or power up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Functional Description
The Cypress CY14V101LA/CY14V101NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 128 K bytes of 8 bits each or 64 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
Logic Block Diagram [1, 2, 3]
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
R
O
W
D
E
C
O
D
E
R
I
N
P
U
T
B
U
F
F
E
R
S
Quatrum Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10 A11
VCC VCCQ VCAP
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A14 - A2
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-53953 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 4, 2011
[+] Feedback
1 page  
CY14V101LA
CY14V101NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14V101LA/CY14V101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14V101LA/CY14V101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by a software address sequence. The
CY14V101LA/CY14V101NA Software STORE cycle is initiated
by executing sequential CE or OE controlled read cycles from six
specific address locations in exact order. During the STORE
cycle an erase of the previous non-volatile data is first performed,
followed by a program of the non-volatile elements. After a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Table 1. Mode Selection
CE WE
HX
LH
LL
LH
OE BHE, BLE[7]
XX
LL
XL
LX
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
A15–A0[8]
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Mode
Not selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
I/O
Output High Z
Output data
Input data
Output data
Output data
Output data
Output data
Output data
Output data
Power
Standby
Active
Active
Active[9]
Notes
7. BHE and BLE are applicable for x16 configuration only.
8.
While there are 17 address lines on the CY14V101LA
Rest of the address lines are don’t care.
(16
address
lines
on
the
CY14V101NA),
only
the
13
address
lines
(A14–A2)
are
used
to
control
software
modes.
9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53953 Rev. *H
Page 5 of 22
[+] Feedback
5 Page 
CY14V101LA
CY14V101NA
AC Switching Characteristics
Over the Operating Range
Parameters [15]
Cypress
Alt
Parameters Parameters
SRAM Read Cycle
tACE
tACS
tRC[16]
tRC
tAA[17]
tAA
tDOE
tOE
tOHA[17]
tOH
tLZCE[18, 19]
tLZ
tHZCE[18, 19]
tHZ
tLZOE[18, 19]
tOLZ
tHZOE[18, 19]
tOHZ
tPU[18]
tPA
tPD[18]
tDBE[[18]
tLZBE[18]
tHZBE[18]
tPS
–
–
–
SRAM Write Cycle
tWC tWC
tPWE
tWP
tSCE
tCW
tSD tDW
tHD tDH
tAW tAW
tSA tAS
tHA tWR
tHZWE[18, 19, 20] tWZ
tLZWE[18, 19]
tOW
tBW –
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
25 ns
Min Max
– 25
25 –
– 25
– 12
3–
3–
– 10
0–
– 10
0–
– 25
– 12
0–
– 10
25 –
20 –
20 –
10 –
0–
20 –
0–
0–
– 10
3–
20 –
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [16, 17, 21]
tRC
Address
Address Valid
tAA
45 ns
Min Max
– 45
45 –
– 45
– 20
3–
3–
– 15
0–
– 15
0–
– 45
– 20
0–
– 15
45 –
30 –
30 –
15 –
0–
30 –
0–
0–
– 15
3–
30 –
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
15.
Test conditions assume signal transition time of 1.8 ns or less,
IOL/IOH and load capacitance shown in Figure 3 on page 10.
timing
reference
levels
of
VCCQ/2,
input
pulse
levels
of
0
to
VCC
Q(typ),
and
output
loading
of
the
specified
16. WE must be HIGH during SRAM read cycles.
17. Device is continuously selected with CE, OE and BHE / BLE LOW.
18. These parameters are guaranteed by design and are not tested.
19. Measured ±200 mV from steady state output voltage.
20. If WE is low when CE goes low, the outputs remain in the high-impedance state.
21. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-53953 Rev. *H
Page 11 of 22
[+] Feedback
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY14V101LA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY14V101LA | 1-Mbit (128 K x 8/64 K x 16) nvSRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |