CY14B256I Datasheet PDF - Cypress Semiconductor
| Part Number | CY14B256I | |
| Description | 256-Kbit (32 K x 8) Serial (I2C) nvSRAM | |
| Manufacturers | Cypress Semiconductor | |
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CY14C256I
CY14B256I, CY14E256I
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
with Real Time Clock
256-Kbit (32 K × 8) Serial (I2C) nvSRAM with Real Time Clock
Features
■ 256-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 32 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
❐
RECALL
RECALL)
to
or
SRAM initiated on power-up (Power-Up
by I2C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 °C
■ Real Time Clock (RTC)
❐ Full-featured RTC
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Backup power fail indication
❐ Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.45 µA (typical)
■ High-speed I2C interface
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast mode Plus 1 MHz speed
❐ High speed: 3.4 MHz
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for one-quarter, one-half, or entire
array
■ I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Low power consumption
❐ Average active current of 1 mA at 3.4 MHz operation
❐ Average standby mode current of 250 µA
❐ Sleep mode current of 8 µA
■ Industry standard configurations
❐ Operating voltages:
• CY14C256I : VCC = 2.4 V to 2.6 V
• CY14B256I : VCC = 2.7 V to 3.6 V
• CY14E256I : VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C256I/CY14B256I/CY14E256I combines a
256-Kbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
QuantrumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
X in RTC Control Logic
INT/SQW
Registers
Xout Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-65230 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 5, 2011
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CY14C256I
CY14B256I, CY14E256I
Data Validity
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH: START and STOP condition. The
START and STOP conditions are generated by the master to
signal the beginning and end of a communication sequence on
the I2C bus.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I2C begins
with the master generating a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
If a Repeated START condition is generated instead of a STOP
condition, the bus continues to be busy. The ongoing transaction
on the I2C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
handbook, full pagewidth
SDA
SCL
SP
START Condition
STOP Condition
Figure 4. Data Transfer on the I2C Bus
P
MSB
Acknowledgement
signal from slave
Acknowledgement Sr
signal from receiver
SCL
S
or
Sr
1
START or
Repeated START
condition
2
789
ACK
Byte complete,
interrupt within slave
1 2 3-8
9
ACK
Clock line held LOW while
interrupts are serviced
Sr
or
P
STOP or
Repeated START
condition
Byte Format
Each operation in I2C is done using 8-bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
Acknowledge / No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I2C bus needs a response with an ACK signal
by the receiver to continue the operation. Failing to do so is
considered as a NACK state. NACK is the state where receiver
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
■ The master did not receive valid data due to noise.
■ The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE
operation in these cases:
■ nvSRAM did not receive valid data due to noise.
■ The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Document #: 001-65230 Rev. *B
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| Information | Total 41 Pages | |
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