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What is CY14E064PA?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "64-Kbit (8 K x 8) SPI nvSRAM".


CY14E064PA Datasheet PDF - Cypress Semiconductor

Part Number CY14E064PA
Description 64-Kbit (8 K x 8) SPI nvSRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY14C064PA
CY14B064PA
CY14E064PA
64-Kbit (8 K × 8) SPI nvSRAM
with Real Time Clock
64-Kbit (8 K × 8) SPI nvSRAM with Real Time Clock
Features
64-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 8 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power Up RECALL)
or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real time clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 µA (typical)
40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and read (with special fast read
instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 250 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C064PA : VCC = 2.4 V to 2.6 V
• CY14B064PA : VCC = 2.7 V to 3.6 V
• CY14E064PA : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14X064PA combines a 64 Kbit nvSRAM[1] with
a full-featured RTC in a monolithic integrated circuit with serial
SPI interface. The memory is organized as 8 K words of 8 bits
each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
You can also initiate the STORE and RECALL operations
through SPI instruction.
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacture ID/
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantrumTrap
8Kx8
SRAM
8Kx8
STORE
RECALL
RDRTC/WRTC
WRSR/RDSR/WREN
Status Register
Xin
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-68249 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 6, 2011
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CY14E064PA equivalent
CY14C064PA
CY14B064PA
CY14E064PA
to complete the Store. This will corrupt the data stored in
nvSRAM, Status Register as well as the serial number and it will
unlock the SNL bit. To resume normal functionality, the WRSR
instruction must be issued to update the nonvolatile bits BP0,
BP1, and WPEN in the Status Register.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical
Characteristics on page 32 for the size of the VCAP.
Figure 2. AutoStore Mode
VCC
0.1uF
VCC
CS VCAP
VSS
VCAP
Software STORE Operation
Software STORE allows the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction regardless of whether or not a
write has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready/Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14X064PA is used to control and
acknowledge STORE operations. If no STORE/RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, the CY14X064PA
conditionally initiates a STORE operation after tDELAY duration.
A STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW. The HSB pin also acts as an open drain
driver (internal 100 kweak pull-up resistor) that is internally
driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 kpull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. In CY14X064PA, a
RECALL may be initiated in two ways: Hardware RECALL,
initiated on power-up and Software RECALL, initiated by a SPI
RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. In
CY14X064PA, this can be done by issuing a RECALL instruction
in SPI.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled in CY14X064PA by using the ASDISB instruction. If
this is done, the nvSRAM does not perform a STORE operation
at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14X064PA comes from the factory with AutoStore
Enabled. If AutoStore is disabled and VCAP is not required, then
the VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power Up RECALL operation cannot
be disabled in any case.
Document #: 001-68249 Rev. *A
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Featured Datasheets

Part NumberDescriptionMFRS
CY14E064PAThe function is 64-Kbit (8 K x 8) SPI nvSRAM. Cypress SemiconductorCypress Semiconductor

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