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PDF CY2XP21 Data sheet ( Hoja de datos )
| Número de pieza | CY2XP21 | |
| Descripción | 125 MHz LVPECL Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY2XP21
125 MHz LVPECL Clock Generator
Features
■ One LVPECL Output Pair
■ Output Frequency: 112 MHz to 140 MHz
■ External Crystal Frequency: 22.4 MHz to 28 MHz
■ Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal
(1.875 MHz to 20 MHz): 0.4 ps (Typical)
■ Pb-free 8-Pin TSSOP Package
■ Supply Voltage: 3.3V or 2.5V
■ Commercial and Industrial Temperature Ranges
Logic Block Diagram
Functional Description
The CY2XP21 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate a
125 MHz clock, which is ideal for 10 Gb Ethernet applications. It
also produces an output frequency that is five times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter. The CY2XP21
has a crystal oscillator interface input and one LVPECL output
pair.
E xt ernal
Cryst al
XIN
CR YS TAL
OSCILLATOR
X OU T
LOW -N OISE
PLL
OUTPU T
D IV IDE R
CLK
CLK#
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8 VDD
7 CLK
6 CLK#
5 NC
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number Pin Name
1, 8 VDD
2 VSS
3, 4 XOUT, XIN
5 NC
6,7 CLK#, CLK
I/O Type
Power
Power
XTAL output and input
LVPECL output
Description
3.3V or 2.5V power supply
Ground
Parallel resonant crystal interface
No Connect
Differential Clock Output
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-52849 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 15, 2009
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PRELIMINARY
CY2XP21
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 8 illus-
trates a typical filtering scheme. Since all the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
V DD
(Pin 8)
VDD
(Pin 1)
3.3V
00..10μ1FµF 10µF
Figure 9. LVPECL Output Termination
3.3V
CLK
Z0 = 50Ω
125Ω 125Ω
CLK#
Z0 = 50Ω
84Ω 84Ω
IN
Crystal Interface
The CY2XP21 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are deter-
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
thus layout dependent.
Figure 10. Crystal Input Interface
Termination for LVPECL Output
The CY2XP21 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
to VDD–2.0V. This same termination voltage can also be used for
VDD = 2.5V operation, or it can be terminated to VDD-1.5V. Note
that it is also possible to terminate with 50 ohms to ground (VSS),
but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the desti-
nation device. To avoid reflections, trace characteristic
impedance (Z0) should match the termination impedance.
Figure 9 shows a standard termination scheme.
X1
18 pF Parallel
Crystal
XIN
C1
30 pF
Device
XOUT
C2
27 pF
Board Layout and NC Pin
Pin 5 (NC) does not perform any function on the CY2XP21.
Although not used electrically, it is very useful for heat dissi-
pation. For this reason, users are advised to connect pin 5 to
either a VDD or VSS plane. This helps to lower the thermal resis-
tance of the board / package combination, thus reducing the die
temperature.
Document #: 001-52849 Rev. *A
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