PDF CY2DP1510 Data sheet ( Hoja de datos )

Número de pieza	CY2DP1510
Descripción	1:10 LVPECL Fanout Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features ■ Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to 10 LVPECL output pairs ■ 40-ps maximum output-to-output skew ■ 600-ps maximum propagation delay ■ 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) ■ Up to 1.5-GHz operation ■ 32-Pin thin quad flat pack (TQFP) package ■ 2.5-V or 3.3-V operating voltage[1] ■ Commercial and industrial operating temperature range Logic Block Diagram VDD VSS IN0 IN0# IN1 IN1# IN_SEL VBB 100k Functional Description The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz. VDD Q0 Q0# Q1 Q1# Q2 Q2# Q3 Q3# Q4 Q4# Q5 Q5# Q6 Q6# Q7 Q7# Q8 Q8# Q9 Q9# Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4NUu.nmebt er: 001-55566 Rev. G • San Jose, CA 95134-1709 • 408-943-2600 Revised February 25, 2011 [+] Feedback 1 page CY2DP1510 DC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition Min Max Unit IDD Operating supply current All LVPECL outputs floating (internal IDD) – 120 mA VIH1 Input high voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# – VDD + 0.3 V VIL1 Input low voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# –0.3 – V VIH2 VIL2 VIH3 VIL3 VID[3] VICM IIH IIL VOH VOL VBB RP CIN Input high voltage, IN_SEL Input low voltage, IN_SEL Input high voltage, IN_SEL Input low voltage, IN_SEL Input differential amplitude Input common mode voltage Input high current, All inputs Input low current, All inputs LVPECL output high voltage LVPECL output low voltage Output reference voltage Internal pull-down resistance Input capacitance VDD = 3.3 V VDD = 3.3 V VDD = 2.5 V VDD = 2.5 V See Figure 2 on page 7 See Figure 2 on page 7 Input = VDD[4] Input = VSS[4] Terminated with 50 Ω to VDD – 2.0[5] Terminated with 50 Ω to VDD – 2.0[5] 0 to 150 μA output current IN_SEL pin Measured at 10 MHz; per pin 2.0 –0.3 VDD + 0.3 0.8 1.7 –0.3 VDD + 0.3 0.7 0.4 1.0 0.5 VDD – 0.2 – 150 –150 – VDD – 1.20 VDD – 0.70 VDD – 2.0 VDD – 1.63 VDD – 1.40 VDD – 1.16 60 140 –3 V V V V V V μA μA V V V kΩ pF Notes 3. VID minimum of 400 mV is required to meet all output AC electrical specifications. The device is functional with VID minimum of greater than 200 mV. 4. Positive current flows into the input pin, negative current flows out of the input pin. 5. Refer to Figure 3 on page 7. Document Number: 001-55566 Rev. G Page 5 of 13 [+] Feedback 5 Page Acronyms Table 2. Acronyms Used in this Document Acronym ESD HBM JEDEC LVDS LVCMOS LVPECL LVTTL OE RMS TQFP Description electrostatic discharge human body model Joint electron devices engineering council low-voltage differential signal low-voltage complementary metal oxide semiconductor low-voltage positive emitter-coupled logic low-voltage transistor-transistor logic Output enable root mean square thin quad flat pack CY2DP1510 Document Conventions Table 3. Units of Measure Symbol °C dBc GHz Hz KΩ µA µF µs mA ms mV MHz ns Ω pF ps V W Unit of Measure degree Celsius decibels relative to the carrier giga hertz hertz kilo ohm microamperes micro Farad microsecond milliamperes millisecond millivolt megahertz nanosecond ohm pico Farad pico second volts watts Document Number: 001-55566 Rev. *G Page 11 of 13 [+] Feedback 11 Page

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