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What is STR-W6253D?

This electronic component, produced by the manufacturer "Allegro Microsystems", performs the same function as "60 W-Universal Input/90 W-230 Vac Input PWM Switching Regulators".


STR-W6253D Datasheet PDF - Allegro Microsystems

Part Number STR-W6253D
Description 60 W-Universal Input/90 W-230 Vac Input PWM Switching Regulators
Manufacturers Allegro Microsystems 
Logo Allegro Microsystems Logo 


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STR-W6253D
60W-Universal Input/90W-230 Vac Input
PWM Switching Regulators
Features and Benefits
Overcurrent protection (OCP) with ac input voltage
compensation function; no additional peripheral circuits
required—minimizes dependency of OCP on ac input
Overload protection (OLP) with integrated timer reduces
power stress (temperature rise) at overload condition,
requires no peripheral components
Avalanche-guaranteed MOSFET improves device
capability of withstanding excess surge voltage,
providing a simple surge absorber circuit without
breakdown voltage derating
Start-up circuit eliminates the need for a start-up resistor,
and helps to reduce input power consumption
Continued on the next page…
Package: TO-220
Description
The STR-W6200D series are current-mode PWM ICs that
incorporate controller chips. These devices are manufactured
using a proprietary high-voltage BCD process, and avalanche-
guaranteed MOSFETs. These elements allow power supply
systems designs that are highly reliable and simple, with fewer
peripheral components. These ICs also provide Auto-Burst
mode operation, which lowers input power requirements at
light loads, and improves efficiency over the entire load range
and universal-input range.
Applicatons include:
TV set top box
LCD PC monitor, LCD TV
Printer, scanner
General consumer, PC, and industrial applications
requiring SMPS power supply with standby mode
Not to scale
Functional Block Diagram
VCC
UVLO
15.5 V/ 8.9 V
REG
VREG
PWM OSC
DMAX 75%
SQ
R
28.5 V OVP
7.1 V ELP
TSD
7.1 V
RST
R
SQ
RQ
S
STARTUP
Istartup
=1.6 mA
DRV
FM/ELP
12 V
FB
Frequency
Modulation
7.8 V
160 μA
S2 Q
OLP
CK
tOLP = S1
tFM×32 R
Slope
Compensation
OCP
Drain Peak
Current
Compensation
Feedback
Control
LEB
www.DataSheet4U.com
28103.53
D/ST
S/OCP
GND

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STR-W6253D equivalent
STR-W6253D
60W-Universal Input/90W-230 Vac Input
PWM Switching Regulators
ELECTRICAL CHARACTERISTICS valid at VCC = 18 V, TA = 25°C, unless otherwise specified
Characteristic
Symbol Terminal
Test Conditions
Power Supply Start-up Operation
Operation Start Voltage
VCC(ON)
Operation Stop Voltage
VCC(OFF)
Circuit Current in Operation
ICC(ON)
4-5
(VCC voltage at which operation starts) Measurement
circuit 1, VCC = 0 through 13.9 through 17.1 V
4-5
(VCC voltage at which operation stops) Measurement
circuit 1, VCC = 17.1 through 9.8 to 8.0 V
4-5
(Inflow current into VCC terminal in oscillation)
Measurement circuit 1
Circuit Current in Non-Oscillation
ICC(STOP)
4-5
(Inflow current into VCC terminal at VFB = 0 V)
Measurement circuit 1
Circuit Current in Non-Operation
Start-up Current
Bias Assist Voltage
ICC(OFF)
Istartup
VBIAS
4-5
(Inflow current into VCC terminal prior to oscillation)
Measurement circuit 1, VCC = 13.8
4-5
(Inflow current into D/ST terminal) Measurement
circuit 7, VCC = 0, D/ST = 450 V
(VCC voltage at which Istartup starts, and IstartupBias
4-5 begins) Measurement circuit 7, VCC = 17.1 through
13.6 to 16.8 V
Operating Characteristics
FM/ELP High Threshold Voltage
VFM(H)
7-5
(FM/ELP terminal voltage at which IFM changes from
–13 μA to 13 μA) Measurement circuit 2
FM/ELP Low Threshold Voltage
FM/ELP Voltage Hysteresis
FM/ELP Outflow Current1
VFM(L)
VFMhys
IFMsrc
7-5
(FM/ELP terminal voltage at which IFM changes from
13 μA to –13 μA) Measurement circuit 2
7-5 (VFM(H) – VFM(L)) Measurement circuit 2
7-5
(FM/ELP terminal outflow current at VFM = VFM(L))
Measurement circuit 2
FM/ELP Inflow Current1
Average Switching Frequency
IFMsink
fOSC(av)
7-5
(FM/ELP terminal inflow current at VFM = VFM(H))
Measurement circuit 2
1-5
(D/ST terminal average oscillation frequency)
Measurement circuit 2
Frequency Jitter Deviation
Maximum Duty Cycle
f
DMAX
1-5 fOSC (peak-to-peak) Measurement circuit 2
1-5
(Maximum width of the low portion of the D/ST
terminal waveform) Measurement circuit 2
FB Maximum Feedback Current1
IFB(MAX)
6-5
(FB terminal outflow current at VFB = 0 V)
Measurement circuit 3
Burst Threshold Voltage
Slope Compensation Start-up
Duty Cycle
Vburst(th)
DSLP
Set VFM = 0 V and decrease VFB (Vburst(th) is the FB
6-5 terminal voltage level at which D/ST changes from
low to high) Measurement circuit 3
6-5
DSLP = (t3 / t4) × 100 (see figure for measurement
circuit 4 for values of t) Measurement circuit 4
Slope Compensation Rate
SLP
6-5
SLP = 0.02 / (t2 – t1) (see figure for measurement
circuit 4 for values of t) Measurement circuit 4
Min.
13.9
8.0
–0.9
13.6
4.0
2.4
1.4
–17.4
8.6
60
4.8
71
–220
0.99
–22
Typ.
15.5
8.9
1.4
0.8
5
–1.6
15.2
4.5
2.8
1.7
–13
13
67
6.9
75
–160
1.10
27
–17
Max
17.1
9.8
2.8
1.3
20
–2.3
16.8
5.0
3.2
1.8
–8.6
17.4
74
9
79
–100
1.21
–12
Units
V
V
mA
mA
μA
mA
V
V
V
V
μA
μA
kHz
kHz
%
μA
V
%
mV/μs
Continued on next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5


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STR-W6253D datasheet


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