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PDF CY26049-36 Data sheet ( Hoja de datos )
| Número de pieza | CY26049-36 | |
| Descripción | Global Communications Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY26049-36
FailSafe™ PacketClock™ Global Communications
Clock Generator
Features
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• Output frequencies selectable and/or programmed to
standard communication frequencies
• Low-jitter, high-accuracy outputs
• Commercial and Industrial operation
• 3.3V ± 5% operation
• 16-lead TSSOP
Benefits
• Integrated high-performance PLL tailored for telecom-
munications frequency synthesis eliminates the need
for external loop filter components
Logic Block Diagram
• When reference is in range, SAFE pin is driven high.
• When reference is off, DCXO maintains clock outputs.
SAFE pin is low.
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Selectable output clock rates include T1/DS1, E1,
T3/DS3, E3, and OC-3.
• Works with commonly available, low-cost 18.432-MHz
crystal
• Zero-ppm error for all output frequencies
• Performance guaranteed for applications that require
an extended temperature range
• Compatible across industry standard design platforms
• Industry standard package with 6.4 x 5.0 mm2 footprint
and a height profile of just 1.1 mm.
external pullable crystal
(18.432 MHz)
XIN XOUT
Input reference
(typical 8 kHz)
ICLK
FAILSAFETM
CONTROL
DIGITAL
CONTROLLED
CRYSTAL
OSCILLATOR
PHASE
LOCKED
LOOP
OUTPUT
DIVIDERS
CLK
CLK/2
FS[3:0]
frequency select
Pin Configuration
www.DataSheet4U.com
SAFE
High=ICLK detected
CY26049-36
16-pin TSSOP
Top View
ICLK 1
8K 2
FS1 3
FS2 4
VDD 5
VSS 6
CLK/2 7
XIN 8
16 NC
15 CLK
14 FS0
13 FS3
12 VDD
11 VSS
10 SAFE
9 XOUT
8K
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07415 Rev. *C
Revised July 16, 2004
1 page  
CY26049-36
DC Electrical Specifications (Industrial Temp: –40° to 85°C)
Parameter
IOH
IOL
VIH
VIL
IIH
IIL
CIN
IOZ
IDD
Description
Output High Current
Output Low Current
Input High Voltage
Input High Voltage
Input High Current
Input Low Current
Input Capacitance
Output Leakage Current
Supply Current
Test Conditions
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD = 3.3V (sink)
CMOS Levels
CMOS Levels
VIH = VDD
VIL = 0V
High Z[1] output
CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 0100
CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 1101
Min.
10
10
0.7
–
–
–
–
–
–
–
Typ.
20
20
–
–
5
5
–
±5
–
–
Max.
–
–
–
0.3
10
10
7
–
50
35
Unit
mA
mA
VDD
VDD
µA
µA
pF
µA
mA
mA
AC Electrical Specifications (Commercial Temp: 0° to 70° C and Industrial Temp: –40° to 85°C)
Parameter
Description
Test Conditions
Min.
fICLK-E
fICLK-B
LR
Frequency, Input Clock
Frequency, Input Clock
FailSafe Lock Range[3]
Input Clock Frequency, External Mode
Input Clock Frequency, Buffer Mode
Range of reference ICLK for Safe = High
–
10
–250
DC = t2/t1
TPJIT1
Output Duty Cycle
Duty Cycle defined in Figure 1, measured at 50% of VDD
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
RMS Period Jitter, RMS
45
–
–
TPJIT2
Clock Jitter; output <5 MHz Period Jitter, Peak to Peak, 10,000 periods
RMS Period Jitter, RMS
–
–
t6
tfs_lock
PLL Lock Time
Failsafe Lock Time
Time for PLL to lock within ± 150 ppm of target frequency
Time for PLL to lock to ICKL (outputs phase aligned with
ICKL and Safe = High)
–
–
ferror
ER
EF
Frequency Synthesis Error
Rising Edge Rate
Falling Edge Rate
Actual mean frequency error vs. target
Output Clock Edge Rate, Measured from 20% to 80% of
VDD, CLOAD = 15 pF See Figure 2.
Output Clock Edge Rate, Measured from 20% to 80% of
VDD, CLOAD = 15 pF See Figure 2.
–
0.8
0.8
Typ.
8.00
–
–
50
–
–
–
–
–
–
0
1.4
1.4
Max. Unit
– kHz
60 MHz
+250 ppm
55 %
250 ps
50 ps
500 ps
100 ps
3 ms
7s
– ppm
2 V/ns
2 V/ns
Voltage and Timing Definitions
CLK
t1
t2
50%
50%
www.DataSheet4U.com
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
80%
t4
CLK
20%
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Note:
3. Dependent on crystals chosen and crystal specs.
Document #: 38-07415 Rev. *C
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