ABB0205 Datasheet PDF - Abracon Corporation
Part Number | ABB0205 | |
Description | Low Skew Output Buffer | |
Manufacturers | Abracon Corporation | |
Logo | ||
There is a preview and ABB0205 download ( pdf file ) link at the bottom of this page. Total 6 Pages |
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Low Skew Outpwwuwt.DBatuaSfhfeeet4rU.com
FEATURES
PIN CONFIGURATION
• Frequency range 25 ~ 60MHz.
• Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to the
outputs (up to 100kHz SST modulation).
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
• Less than 150 ps cycle - cycle jitter.
• Output Enable function tri-state outputs.
• 3.3V operation.
• Available in 8-Pin 150mil SOIC.
DESCRIPTION
REF
CLK2
CLK1
GND
1
2
3
4
8 CLKOUT
7 CLK4
6 VDD
5 CLK3
Remark
If REF clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
The ABB0205 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in 8-pin SOIC package. It
has four outputs that are synchronized with the input.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than ±350 ps, the device
acts as a zero delay buffer.
BLOCK DIAGRAM
REF PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1
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ABB0205
Low Skew Outwpwuw.tDaBtaSuhfeefte4Ur.com
Output-Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the
PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained
from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will
maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; if the
CLK(0-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time,
but difference loads cause them to have different rise times and different times crossing
the measurement thresholds.
REF
CLKOUT
CLK(1-4)
Zero Delay
REF input and all outputs loaded equally
REF
CLKOUT
CLK(1-4)
Advanced
REF input and CLK(1-4) outputs loaded equally,
with CLK(1-4) less loaded than CLKOUT.
REF
CLKOUT
CLK(1-4)
Delayed
REF input and CLK(1-4) outputs loaded equally, with
CLK(1-4) more loaded than CLKOUT.
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ABB0205 electronic component. |
Information | Total 6 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ ABB0205.PDF Datasheet ] |
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